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PACDN002Q: Description17 CHANNEL ESD PROTECTION ARRAY; File Size112KB，3 Pages; ManufacturerCALMIRCO; Websitehttp://www.calmicro.com/

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PACDN002Q Overview

17 CHANNEL ESD PROTECTION ARRAY

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CALIFORNIA MICRO DEVICES

PAC DN002

Applications

Parallel printer port protection

ESD protection for sensitive

electronic equipment

Drop-in replacement for PDN 002

17 CHANNEL ESD PROTECTION ARRAY

Features

17-channel ESD protection

8kV contact discharge ESD protection per

IEC 61000-4-2

15kV ESD protection (HBM)

Low loading capacitance, 5.5pF typ.

20-pin SOIC or QSOP package

Product Description

The PAC DN002 is a diode array designed to provide 17 channels of ESD protection for electronic components or

sub-systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V

) or

negative (V

) supply. The PAC DN002 will protect against ESD pulses up to 15KV Human Body Model.

This device is particularly well-suited to provide additional ESD protection for parallel printer ports. It exhibits low

loading capacitance for all signal lines.

ABSOLUTE MAXIMUM RATINGS

SCHEMATIC CONFIGURATION

Diode Forward DC Current

(Note 1)

20mA

Storage Temperature

-65 C to 150

Operating Temperature Range

-20°C to 85°C

DC Voltage at any Channel Input V

-0.5V to V

+0.5V

Note 1: Only one diode conducting at a time.

STANDARD SPECIFICATIONS

STANDARD SPECIFICATI

Parameter

Para

ati

eter

upply Voltage (V - V )

Min.

Oper

ng S

ing

ent

(

age (V

2 .0 V, T = 25°C

Cu r

up y

) = 1

- V

)

ode

ent (V

tage, I

= 20

0 V,

T =

5°

5°C

0.65 V

ppl

ard Vol

- V

)

1 2 .

0.65 V

D iode Forward Voltage, I

= 20mA, T = 25°C

ESD Protection

Voltage at any Channel Input

Human Body Model, Method 3015

(See Note 2, 3)

±15KV

Human Body Model, Method 3015

(See Note 2, 3)

±15KV

±8KV

Contact Discharge per IEC 1000-4-2 (

See Note 4)

±8KV

Contact D ischarge per IEC 1000-4-2 (

See Note 4)

Channel Clamp Voltage under ESD test conditions

specified above, T = 25°C (

Notes 2,3,4)

specified above, T = 25°C (

Notes 2,3,4)

Positive transients

Negative transients

Channel Leakage Current, T = 25°C

Channel Input Capacitance (Measured @ 1 MHz)

= 12V, V

= 0V, V

= 6 V (

See Note 4)

Package Power Rating

Note 2:

Note 3:

Note 4:

Typ.

Max.

12 0 V

µA

1.0 V

±0.1 µA

5.5pF

+ 13.0 V

- 13.0 V

±1.0 µA

12pF

1.00W

From I/O pins to V

or V

only. V

bypassed to V

with 0.2

F ceramic capacitor.

Human Body Model per MIL-STD-883, Method 3015, C

Discharge

=100pF, R

Discharge

=1.5K

Ω

, V

=12V, V

=GND.

This parameter is guaranteed by characterization.

11/99

C0270498D

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

CALIFORNIA MICRO DEVICES

PAC DN002

Similarly for negative ESD pulses, parasitic series inductance from the V

pin to the ground rail will lead to drastically

increased negative voltage on the line being protected.

Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies

exhibit a much higher output impedance to fast transient current spikes. In the V

equation above, the V

Supply

term, in

reality, is given by (V

+ I

esd

x R

out

), where V

and R

out

are the nominal supply DC output voltage and effective output

impedance of the power supply respectively. As an example, a R

out

of 1 ohm would result in a 10V increment in V

for a

peak I

esd

of 10A.

To mitigate these effects, a high frequency bypass capacitor should be connected between the V

pin of the ESD Protection

Array and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge

transferred by the ESD pulse with minimal change in V

. Typically a value in the 0.1 µF to 0.2 µF range is adequate for

IEC-61000-4-2 level 4 contact discharge protection (8KV). For higher ESD voltages, the bypass capacitor should be

increased accordingly. Ceramic chip capacitors mounted with short printed circuit board traces are good choices for this

application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection,

connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance

inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply

voltage.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V

pin of the

Protection Array as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray

series inductance.

11/99

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

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