K9E2G08B0M
Document Title
256M x 8 Bits NAND Flash Memory
Advanced
FLASH MEMORY
Revision History
Revision No. History
0.0
0.1
Draft Date
Nov. 8th 2004
Nov. 22th 2004
Remark
Advanced
Preliminary
Initial issue.
1.Note1 of Program/Erase characteristics is added
2.Technical note is changed
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9E2G08B0M
Advanced
FLASH MEMORY
256M x 8 Bits NAND Flash Memory
PRODUCT LIST
Part Number
K9E2G08B0M-Y,P
K9E2G08B0M-V,F
Vcc Range
2.5V ~ 2.9V
Organization
X8
PKG Type
TSOP1
WSOP1
FEATURES
•
Voltage Supply : 2.5V ~ 2.9V
•
Organization
- Memory Cell Array : (256M + 8,192K)bits x 8bits
- Data Register : (512 + 16)bits x 8bits
•
Automatic Program and Erase
- Page Program : (512 + 16)bits x 8bits
- Block Erase : (16K + 512)Bytes
•
Page Read Operation
- Page Size : (512 + 16)Bytes
- Random Access
: 15µs(Max.)
- Serial Page Access : 50ns(Min.)
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Intelligent Copy-Back
•
Unique ID for Copyright Protection
•
Package
- K9E2G08B0M-YCB0/YIB0
48 - Pin TSOP I (12 X 20 / 0.5 mm pitch)
- K9E2G08B0M-VCB0/VIB0
48 - Pin WSOP I (12 X 17 X 0.7mm)
- K9E2G08B0M-PCB0/PIB0
48 - Pin TSOP I (12 X 20 / 0.5 mm pitch)- Pb-free Package
- K9E2G08B0M-FCB0/FIB0
48 - Pin WSOP I (12 X 17 X 0.7mm)- Pb-free Package
GENERAL DISCRIPTION
Offered in 256Mx8bits, the K9E2G08B0M is 2Gbit with spare 64Mbit capacity. The device is offered in 2.7 Vcc. Its NAND cell provides
the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on
the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can be read out at
50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write control automates all program and erase functions including pulse repetition, where required, and internal verification and mar-
gining of data. Even the write-intensive systems can take advantage of the K9E2G08B0M′s extended reliability of 100K program/
erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9E2G08B0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
2
K9E2G08B0M
PIN CONFIGURATION (TSOP1)
K9E2G08B0M-YCB0,PCB0/YIB0,PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Advanced
FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
+0.075
20.00
±0.20
0.787
±0.008
0.20
-0.03
+0.07
#1
0.008
-0.001
0.16
-0.03
+0.07
+0.003
0.50
0.0197
12.00
0.472
0.05
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
3
0.005
-0.001
+0.003
18.40
±0.10
0.724
±0.004
1.20
0.047MAX
K9E2G08B0M
PIN CONFIGURATION (WSOP1)
K9E2G08B0M-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
Advanced
FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
15.40
±0.10
0.58
±0.04
#1
+0.07
-0.03
#48
+0.07
-0.03
0.16
12.40MAX
12.00
±0.10
0.50TYP
(0.50
±
0.06)
0.20
#24
#25
(0.01Min)
0.10
+0.075
-0.035
0
°
~
8
°
0.45~0.75
17.00
±0.20
4
K9E2G08B0M
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
Pin Function
Advanced
FLASH MEMORY
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’Page read’ section of Device operation .
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
OUTPUT BUFFER POWER
V
CC
Q is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected.
CLE
ALE
CE
RE
WE
WP
R/B
VccQ
Vcc
Vss
N.C
DNU
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
5
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