3 Megabit High Speed CMOS SRAM
DPS128X24Bn3
DESCRIPTION:
The DPS128X24Bn3 High Speed SRAM ‘’STACK’’ modules are a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded
packages, or mounted on a 50-pin PGA co-fired ceramic substrate.
The module packs 3-Megabits of low-power CMOS static RAM in
an area as small as 0.463 in
2
, while maintaining a total height as
low as 0.332 inches.
The DPS128X24Bn3 STACK modules contain three individual
128K x 8 SRAMs, each packaged in a hermetically sealed SLCC,
making the modules suitable for commercial, industrial and
military applications.
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC Stack
Straight Leaded
Stack
FEATURES:
•
Organizations Available: 128Kx24, 384Kx8
•
Access Times: 20*, 25, 30, 35, 45ns
•
Fully Static Operation - No clock or refresh required
•
Single +5V Power Supply,
±
10% Tolerance
•
TTL Compatible
•
Common Data Inputs and Outputs
•
Low Data Retention Voltage: 2.0V min.
•
Packages Available:
48 - Pin SLCC Stack
48 - Pin Straight Leaded Stack
48 - Pin ‘’J’’ Leaded Stack
48 - Pin Gullwing Leaded Stack
50 - Pin PGA Dense-Stack
*
Commercial only.
‘’J’’ Leaded
Stack
Dense-Stack
Gullwing
Leaded Stack
30A097-33
REV. C
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
Dense-Pac Microsystems, Inc.
DPS128X24Bn3
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
T
STC
Storage Temperature
T
BIAS
V
DD
V
I/O
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
3
TRUTH TABLE
Unit
°C
°C
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Value
-65 to +150
-55 to +125
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
-0.5 to +7.0
°C
-0.5 to V
DD
+0.5 V
Supply
I/O Pin Current
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4 V
RECOMMENDED OPERATING RANGE
Symbol
Characteristic
V
DD
Supply Voltage
V
IH
Input HIGH Voltage
V
IL
Input LOW Voltage
M/B
Operating
T
A
I
Temperature
C
Min.
4.5
2.2
-0.5
2
-55
-40
0
Typ.
5.0
3
Max. Unit
5.5
V
V
DD
+0.3 V
0.8
V
+25 +125
o
+25
+85
C
+25
+70
CAPACITANCE
4
: T
A
= 25°C, F = 1.0MHz
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
35
15
35
35
15
Unit
Condition
pF
V
IN2
= 0V
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current (3V)
Data Retention
Supply Current (2V)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V
V
DR
= 2V, CE
≥
V
DR
-0.2V
I
OUT
= 8.0mA
I
OUT
= -4.0mA
x8
x24
Typ.*
-
-
150
300
1.2
75
0.21
.105
-
-
2.4
C
Min.
Max.
Min.
I
Max.
M/B
Min.
Max.
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
-15
-10
+15
+10
200
420
15
90
1.2
0.75
0.4
-15
-10
+15
+10
210
420
15
105
1.8
1.2
0.4
-15
-10
+15
+10
230
480
30
105
6.0
5.4
0.4
2.4
2.4
† Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
30A097-33
REV. C
3
DPS128X24Bn3
Dense-Pac Microsystems, Inc.
OUTPUT LOAD
Load
1
2
C
L
30pF
5pF
Parameters Measured
except t
LZ
,t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
t
LZ
, t
HZ
, t
OHZ
, t
OLZ
, and t
WHZ
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
D
OUT
C
L
*
255Ω
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
Data Retention AC Characteristics
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
See Data Retention Waveform
See Data Retention Waveform
8
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
4
30A097-33
REV. C
Dense-Pac Microsystems, Inc.
DPS128X24Bn3
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
8
3
0
10
8
3
25
25
25
10
3
0
12
10
3
30
30
30
15
3
0
15
15
3
35
35
35
20
3
0
20
20
3
45
45
45
25
3
0
25
25
3
* Available in Commercial Only.
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A097-33
REV. C
5
Analogue and Mixed Signal
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