DSC2130
DSC2230
Datasheet
Low-Jitter I
2
C/SPI Programmable LVDS Oscillator
General Description
The DSC2130 and DSC2230 series of
programmable,
high-performance
LVDS
oscillators utilizes a proven silicon MEMS
technology to provide excellent jitter and
stability while incorporating high output
frequency flexibility. DSC2130 and DSC2230
allow the user to modify the output
frequency using I
2
C or SPI interface,
respectively. User can also select from two
pre-programmed default output frequencies
using the control pin.
DSC2130 and DSC2230 are packaged in 14-
pin 3.2x2.5 mm QFN packages and available
in temperature grades from Ext. Commercial
to industrial.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
I
2
C/SPI Programmable Output Freq
Short Lead Times: 2 Weeks
Wide Freq. Range:
o
LVDS Output: 2.3 to 460 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Consumer Electronics
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
Pin #
3
5
6
7
DSC2130 (I
2
C)
NC
SDA
SCL
CS_bar
DSC2230 (SPI)
SCLK
MOSI
MISO
SS
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DSC2130 DSC2230
Page 1
MK-Q-B-P-D-12050106
DSC2130
DSC2230
Low-Jitter I
2
C/SPI Programmable LVDS Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
SCLK
GND
SDA
MOSI
SCL
MISO
CS_bar
SS
Output1+
Output1-
NC
NC
VDD2
VDD
FS
Pin Type
I
NA
NA
I
Power
I
I
O
I
I
O
O
NA
NA
Power
Power
I
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
DSC2130: Leave unconnected or grounded
DSC2230: Serial clock from master
Ground
DSC2130: I
2
C Serial Data
DSC2230: SPI Serial Data from Master to Slave
DSC2130: I
2
C Serial Clock
DSC2230: SPI Serial Data from Slave to Master
DSC2130: I
2
C Chip Select (Active Low)
DSC2230: SPI Slave Select (Active Low)
Positive LVDS Output
Negative LVDS Output
Leave unconnected or grounded
Leave unconnected or grounded
Power Supply
Power Supply
Default output clock frequency bit
Operational Description
The DSC2130/2230 is a LVDS oscillator
consisting of a MEMS resonator and a support
PLL IC.
The LVDS output is generated
through independent 8-bit programmable
dividers from the output of the internal PLL.
DSC2130/2230 allows for easy programming
of the output frequencies using I
2
C/SPI
interface. Upon power-up, the initial output
frequency is controlled by an internal pre-
programmed memory (OTP). This memory
stores all coefficients required by the PLL for
two different default frequencies. The control
pin (FS) selects the initial frequency. Once
the device is powered up, a new output
frequency can be programmed. Programming
details are provided in the
Programming
Guide.
Standard default frequencies are
described in the following sections. Discera
supports customer defined versions of the
DSC2130/2230.
When Enable (pin 1) is floated or connected to
VDD, the DSC2130/2230 is in operational
mode. Driving Enable to ground will disable
both output drivers (hi-impedance mode).
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DSC2130 DSC2230
Page 2
MK-Q-B-P-D-12050106
DSC2130
DSC2230
Low-Jitter I
2
C/SPI Programmable LVDS Oscillator
Output Clock Frequencies
Table 2 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 2. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
C0001
C0002
C0003
C0004
C0005
CXXXX
Freq
(MHz)
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
Select Bit [FS] –
Default is [1]
0
148.352
100
100
148.5
315
1
74.1758
0*
150
148.35
0*
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [1] and
the device will output the associated frequency highlighted in
Bold.
0* – denotes invalid selection, output frequency is not specified.
_____________________________________________________________________________________________________________________________ _________________
DSC2130 DSC2230
Page 3
MK-Q-B-P-D-12050106
DSC2130
DSC2230
Low-Jitter I
2
C/SPI Programmable LVDS Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
V
V
°C
°C
°C
V
40sec max.
Prog Mode
1: I
2
C bus
2: SPI bus
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
DSC2
1
30
F I 2
Package
F: 3.2x2.5mm
-
xxxxx
T
Freq (MHz)
See Freq. table
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
(Unless specified otherwise: T=25° C)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
2
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
3
Output Enable Time
Pull-Up Resistor
4
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
EN pin low – output is disabled
Output Enabled, R
L
=100Ω
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
Min.
2.25
Typ.
21
29
Max.
3.6
23
32
±10
±25
±50
±5
5
Unit
V
mA
mA
ppm
ppm
ms
V
ns
ns
kΩ
0.75xV
DD
-
-
0.25xV
DD
5
20
40
LVDS Outputs
R=100Ω Differential
Single-Ended
t
R
t
F
f
0
SYM
J
PER
J
CC
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
F
O
=156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.3
48
2.5
0.28
0.4
1.7
1.125
350
200
460
52
1.4
50
V
mV
mV
ps
MHz
%
ps
RMS
ps
RMS
2
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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DSC2130 DSC2230
Page 4
MK-Q-B-P-D-12050106
DSC2130
DSC2230
Low-Jitter I
2
C/SPI Programmable LVDS Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
156MHz-LVDS
Phase Jitter (ps RMS)
2.0
212MHz-LVDS
320MHz-LVDS
1.5
410MHz-LVDS
1.0
0.5
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
LVDS Phase jitter (integrated phase noise)
Output Waveform: LVDS
t
R
t
F
Output
Output
80
%
50%
20%
350 mV
830 mv
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
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DSC2130 DSC2230
Page 5
MK-Q-B-P-D-12050106
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