74LVTH543MTCX datasheet, PDF - EEWORLD Datasheet

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74LVTH543MTCX: DescriptionIC registered txrx 8bit 24tssop; Categorylogic logic; File Size64KB，7 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/; Environmental Compliance

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74LVTH543MTCX Overview

IC registered txrx 8bit 24tssop

74LVTH543MTCX Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fairchild
Parts packaging code	TSSOP
package instruction	TSSOP, TSSOP24,.25
Contacts	24
Reach Compliance Code	unknown
Control type	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL
series	LVT
JESD-30 code	R-PDSO-G24
JESD-609 code	e3
length	7.8 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.064 A
Humidity sensitivity level	1
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP24,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	3.7 ns
propagation delay (tpd)	6.6 ns
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
translate	N/A
width	4.4 mm
Base Number Matches	1

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74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs

April 2000

Revised November 2000

74LVTH543

Low Voltage Octal Registered Transceiver

with 3-STATE Outputs

General Description

The LVTH543 octal transceiver contains two sets of D-type

latches for temporary storage of data flowing in either

direction. Separate Latch Enable and Output Enable inputs

are provided for each register to permit independent con-

trol of inputting and outputting in either direction of data

flow.

The LVTH543 data inputs include bushold, eliminating the

need for external pull-up resistors to hold unused inputs.

This octal registered transceiver is designed for low-volt-

age (3.3V) V

applications, but with the capability to pro-

vide a TTL interface to a 5V environment. The LVTH543 is

fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs

Live insertion/extraction permitted

Power Up/Down high impedance provides glitch-free

bus loading

Outputs source/sink

−

32 mA/

64 mA

Functionally compatible with the 74 series 543

Latch-up performance exceeds 500 mA

ESD performance:

Human-body model

2000V

Machine model

200V

Charged-device model

1000V

Ordering Code:

Order Number

74LVTH543WM

74LVTH543MTC

Package Number

M24B

MTC24

Package Description

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

OEAB, OEBA

LEAB, LEBA

CEAB, CEBA

–A

Description

Output Enable Inputs

Latch Enable Inputs

Chip Enable Inputs

Side A Inputs or

3-STATE Outputs

–B

Side B Inputs or

3-STATE Outputs

DS012448

www.fairchildsemi.com

74LVTH543MTCX Related Products

	74LVTH543MTCX	74LVTH543WMX
Description	IC registered txrx 8bit 24tssop	IC registered txrx 8bit 24soic
Is it Rohs certified?	conform to	conform to
Maker	Fairchild	Fairchild
Parts packaging code	TSSOP	SOIC
package instruction	TSSOP, TSSOP24,.25	SOP, SOP24,.4
Contacts	24	24
Reach Compliance Code	unknown	compliant
Control type	INDEPENDENT CONTROL	INDEPENDENT CONTROL
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL
series	LVT	LVT
JESD-30 code	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e3	e3
length	7.8 mm	15.4 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
MaximumI(ol)	0.064 A	0.064 A
Humidity sensitivity level	1	1
Number of digits	8	8
Number of functions	1	1
Number of ports	2	2
Number of terminals	24	24
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP
Encapsulate equivalent code	TSSOP24,.25	SOP24,.4
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
method of packing	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	3.7 ns	3.7 ns
propagation delay (tpd)	6.6 ns	6.6 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	2.65 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	BICMOS	BICMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
translate	N/A	N/A
width	4.4 mm	7.5 mm
Base Number Matches	1	1

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