CY39200Z208-83MBI datasheet, PDF

Datasheet> All Categories > CY39200Z208-83MBI

Preview

CY39200Z208-83MBI: DescriptionCPLDs at FPGA Densities; File Size1MB，86 Pages; ManufacturerCypress Semiconductor

Download Datasheet View All

CY39200Z208-83MBI Overview

CPLDs at FPGA Densities

Preview

Download Datasheet

View All

Delta39K™ ISR™

CPLD Family

CPLDs at FPGA Densities™

Features

• High density

— 30K to 200K usable gates

— 512 to 3072 macrocells

— 136 to 428 maximum I/O pins

— Twelve dedicated inputs including four clock pins,

four global I/O control signal pins and four JTAG

interface pins for boundary scan and reconfig-

urability

Embedded memory

— 80K to 480K bits embedded SRAM

• 16K to 96K bits of (dual-port) channel memory

High speed – 233-MHz in-system operation

AnyVolt™ interface

— 3.3V, 2.5V,1.8V, and 1.5V I/O capability

Low-power operation

— 0.18-mm six-layer metal SRAM-based logic process

— Full-CMOS implementation of product term array

— Standby current as low as 5mA

• Simple timing model

— No penalty for using full 16 product terms/macrocell

— No delay for single product term steering or sharing

• Flexible clocking

— Spread Aware™ PLL drives all four clock networks

• Allows 0.6% spread spectrum input clocks

• Several multiply, divide and phase shift options

— Four synchronous clock networks per device

— Locally generated product term clock

— Clock polarity control at each register

• Carry-chain logic for fast and efficient arithmetic opera-

tions

• Multiple I/O standards supported

— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2

(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+

• Compatible with NOBL™, ZBT™, and QDR™ SRAMs

• Programmable slew rate control on each I/O pin

• User-programmable Bus Hold capability on each I/O pin

• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,

rev. 2.2)

• CompactPCI hot swap ready

• Multiple package/pinout offering across all densities

— 208 to 676 pins in PQFP, BGA, and FBGA packages

— Simplifies design migration across density

— Self-Boot™ solution in BGA and FBGA packages

• In-System Reprogrammable™ (ISR™)

— JTAG-compliant on-board programming

— Design changes do not cause pinout changes

• IEEE1149.1 JTAG boundary scan

•

Development Software

•

Warp

— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context

sensitive editing

— Active-HDL FSM graphical finite state machine editor

— Active-HDL SIM post-synthesis timing simulator

— Architecture Explorer for detailed design analysis

— Static Timing Analyzer for critical path analysis

— Available on Windows



95/98/2000/XP™ and

Windows NT™ for $99

— Supports all Cypress programmable logic products

Delta39K™ ISR CPLD Family Members

Typical

Gates

[1]

16K – 48K

23K – 72K

46K – 144K

77K – 241K

92K – 288K

Cluster

memory

(Kbits)

192

320

384

Channel

memory

(Kbits)

Maximum

I/O Pins

174

218

302

386

428

MAX2

(MHz)

233

222

181

Speed-t

Pin-to-Pin

(ns)

7.2

7.5

8.5

Standby I

[2]

= 25°C

3.3/2.5V

5 mA

10 mA

20 mA

Device

39K30

39K50

39K100

39K165

39K200

Macrocells

512

768

1536

2560

3072

Notes:

1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.

2. Standby I

values are with PLL not utilized, no output load and stable inputs.

Cypress Semiconductor Corporation

Document #: 38-03039 Rev. *H

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised August 1, 2003

Recommended Resources

TDA7230A SD power amplifier circuit diagram

Application circuit of HA1392

Application circuit of TDA2030A-single power supply operation

The sum of two inputs minus the sum of other two inputs circuit

12V, 18V dual-channel regulated power supply circuit

Boiler coal loading machine circuit

How to measure real-time performance of embedded products: When developers choose RTOS for embedded products , real-time performance is one of the most important criteria. The latest research report from embedded market research companies Evans Data and Ventu...; frozenviolet Automotive Electronics

Problems with NK.lib: Hello, seniors! I recently encountered the problem of not being able to connect to NK.lib when compiling the OAL of WINCE5.0. I learned from the help file of PB5.0 that NK.lib is composed of Cefnk.lib...; lssbw Embedded System

Darlington optocoupler, what is the role of the diode in parallel with the transistor: What is the function of the diode in parallel with the transistor in Darlington optocoupler?...; benny512 Power technology

Who can make a two-way signal amplifier repeater?: Make two 315-433 frequency two-way signal amplification repeaters, which can bidirectionally transmit and amplify any 315-433 signal in the air. It is mainly used to transmit the (RFID wireless radio ...; 5305078 RF/Wirelessly

Someone who doesn't understand hardware asks a power supply question: Why doesn't the switching power supply use a magnetic bar for conversion?: I don't know much about hardware. Today, my friend made a DC/DC, which used a transformer wound with a toroidal magnetic core. The winding is very troublesome. I was thinking, if I use a magnetic rod,...; Aragorn Power technology

Causes and Solutions of PCB Deformation: [size=3]When the circuit board is reflowed, it is easy to bend and warp. In serious cases, it may even cause empty soldering and tombstone formation of components. How to overcome this problem? [/size...; ohahaha PCB Design

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components