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ACTS280K/SAMPLE

Description
ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14
Categorylogic    logic   
File Size108KB,3 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet Parametric View All

ACTS280K/SAMPLE Overview

ACT SERIES, 9-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14

ACTS280K/SAMPLE Parametric

Parameter NameAttribute value
Objectid1530484727
Parts packaging codeDFP
package instructionDFP,
Contacts14
Reach Compliance Codeunknown
YTEOL0
seriesACT
JESD-30 codeR-CDFP-F14
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)24 ns
Certification statusNot Qualified
Maximum seat height2.92 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
width6.285 mm

ACTS280K/SAMPLE Preview

TM
ACTS280MS
Radiation Hardened 9-Bit Odd/
Even Parity Generator Checker
Pinouts
14 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
LEAD FINISH C
TOP VIEW
I6 1
I7 2
NC 3
I8 4
EVEN
ODD
GND
5
6
7
14 VCC
13 I5
12 I4
11 I3
10 I2
9 I1
8 I0
January 1996
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96720 and Intersil’ QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 24ns (Max), 16ns (Typ)
14 PIN CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP3-F14
LEAD FINISH C
TOP VIEW
I6
I7
NC
I8
EVEN
ODD
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
I5
I4
I3
I2
I1
I0
Description
The Intersil ACTS280MS is a Radiation Hardened 9-bit odd/even parity
generator checker device. Both odd and even parity outputs are avail-
able for generating or checking parity for words up to 9 bits long. Even
parity is indicated (EVEN output high) when an even number of data
inputs are high. Odd parity is indicated (ODD output high) when an odd
number of data inputs are high. Parity checking for larger words can be
accomplished by tying EVEN output to any input of an additional
ACTS280MS.
The ACTS280MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACTS280MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line Package (D suffix).
Ordering Information
PART NUMBER
5962F9672001VCC
5962F9672001VXC
ACTS280D/Sample
ACTS280K/Sample
ACTS280HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
Spec Number
518827
FN3569.1
ACTS280MS
Functional Diagram
I8 (4)
I7 (2)
I6 (1)
E (5)
I5 (13)
I4 (12)
I3 (11)
O (6)
I2 (10)
I1 (9)
I0 (8)
NC = 3
VDD = 14
GND = 7
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
2
Spec Number
518827
ACTS280MS
Die Characteristics
DIE DIMENSIONS:
88 mils x 88 mils
2.24mm x 2.24mm
METALLIZATION:
Type: AlSi
Metal 1 Thickness: 7.125k
Å
±1.125k
Å
Metal 2 Thickness: 9k
Å
±1k
Å
GLASSIVATION:
Type: SiO
2
Thickness: 8k
Å
±1k
Å
WORST CASE CURRENT DENSITY:
<2.0 x 10
5
A/cm
2
BOND PAD SIZE:
> 4.3 mils x 4.3 mils
> 110µm x 110µm
Metallization Mask Layout
ACTS280MS
(14) VCC
(13) I5
(2) I7
(1) I6
NC (3)
(12) I4
I8 (4)
(11) I3
NC
NC
EVEN (5)
(10) I2
I0 (8)
ODD (6)
GND (7)
I1 (9)
Spec Number
3
518827
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