FX-424
Low Jitter Frequency Translator
Features
•
Quartz-based PLL for Ultra-Low Jitter
•
Frequency Translation up to 850 MHz
•
Accepts up to 4 ext.-muxed clock inputs
•
CMOS / LVDS / LVPECL Inputs compatible
•
Differential LVPECL or LVCMOS Output
•
Lock Detect / Loss of Signal Alarms
•
Output Disable
•
20.3 x 13.7 x 5.1 mm SMT package
•
RoHS/Lead Free Compliant
Description
The FX-424 is a precision quartz-based frequency
translator used to translate an input frequency such
as 8 kHz, 1.544 MHz, 2.048 MHz, 19.44 MHz etc.
to any specific frequency from 1.544 MHz to 850
MHz. The FX-424 can perform either up or down
frequency conversion. The FX-424’s superior jitter
performance is achieved through the use of a
precision VCXO or VCSO. With the use of an
external multiplexer, up to 4 different input clocks
can be translated to a common output frequency.
Applications
•
Wireless Infrastructure
•
10 Gigabit FC
•
10GbE LAN / WAN
•
OADM and IP Routers
•
Test Equipment
•
Military Communications
Figure 1. Functional Block Diagram
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 1 of 9
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 08Dec06
FX-424 Low Jitter Frequency Translator
Table 1. Electrical Performance
Parameter
Frequency
Input Frequency
Capture Range
Output Frequency
Supply
Voltage
Current (No Load)
Input Signal
CMOS
LVPECL
LVCMOS Output (Option
A)
Differential Output (Options
F and P)
Mid Level - LVPECL
Swing - LVPECL
Mid Level - LVDS
Swing - LVDS
Rise Time
Fall Time
Symmetry
SSB Phase Noise,
F
OUT
=
155.52/622.08
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
Jitter Generation
155.52 MHz (12 kHz – 20 MHz BW)
622.08 MHz (12 kHz – 20 MHz BW)
Operating Temperature
1.
2.
3.
4.
5.
6.
Symbol
F
IN
APR
F
OUT
V
CC
I
CC
F
IN
F
IN
Minimum
0.008
±40
1.544
3.13
Typical
Maximum
170
850
Units
MHz
ppm
MHz
V
mA
Notes
1,2,3
1,2,3
1,2,3
2,3
3
2,3
2,3
3.3
45
CMOS
LVPECL
LVCMOS
3.46
60
V
CC
-1.4
450
V
CC
-2.4
250
t
R
t
F
SYM
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
n
Φ
J
Φ
J
T
OP
45
V
CC
-1.25
600
V
CC
-2.3
410
0.5
0.5
50
-64/-27
-95/-55
-123/-85
-143/-110
-146/-130
-146/-146
-146/-146
0.30
0.12
V
CC
-1.0
950
V
CC
-2.5
450
55
V
mV-pp
V
mV-pp
ns
ns
%
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps RMS
ps RMS
2,3
2,3
2,3
2,3
4,5
4,5
2,3
5,6
5, 6
1,3
-40
85
°C
See Standard Frequencies and Ordering Information.
Parameters are tested with production test circuit below (Fig 2).
Parameters are tested at ambient temperature with test limits guard-banded for specified operating temperature.
Measured from 20% to 80% of a full output swing (Fig 3).
Not tested in production, guaranteed by design, verified at qualification.
The FX-424 phase noise and jitter performance can be optimized for specific applications. Please consult with Vectron’s Application
Engineers for more information.
t
R
t
F
SYM
= 100 x t
A
/t
B
V
OH
80%
50%
20%
V
OL
t
A
t
B
Figure 2. Test Circuit
Figure 3. LVPECL Waveform
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 2 of 9
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 08Dec06
FX-424 Low Jitter Frequency Translator
Figure 4. Pin Configuration
Table 2. Pin Out
Pin #
1
2
3
4
5
Symbol
SEL0
SEL1
GND
I/O
I
I
GND
Level
LVTTL
LVTTL
Supply
Function
Input Frequency Select*
Input Frequency Select*
Case and Electrical Ground
Not present
VCXO Control Voltage Monitor
Under locked conditions VMON should be > 0.3V and <3.0V. The input
frequency may be out of range if the voltage exceeds these levels.
Output Disable
Disabled = Logic “1”
Enabled = Logic “0” or no connect
Case and Electrical Ground
Frequency Output
Complementary Frequency Output – Note for LVCMOS option this pad
will be tied to GND.
Lock Detect
Locked = Logic “1”
Loss of Signal = Logic “0”
Case and Electrical Ground
Case and Electrical Ground
Input Frequency. The FX-424 series AC couples the input for handling of
either LVCMOS or LVPECL input signals.
Power Supply Voltage (3.3 V ±5%)
VMON
O
Analog
6
7
8
9
10
11
12
13
14
OD
GND
FOUT
CFOUT
LD
GND
GND
FIN
VCC
I
GND
O
O or
GND
O
GND
GND
I
VCC
LVCMOS
Supply
LVPECL, LVDS,
or LVCMOS
LVPECL, LVDS,
or LVCMOS
LVCMOS
Supply
Supply
LVCMOS or
LVPECL
Supply
* For applications requiring two to four input frequencies, Vectron will assign a unique part number and the Input Frequency versus SEL[1:0]
settings will be provided in a Specification Control Drawing. For single input configurations it is recommended that SEL0 and SEL1 are tied
to ground.
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 3 of 9
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 08Dec06
FX-424 Low Jitter Frequency Translator
Outline Diagram
mm
[inches]
0.79
[0.031]
20.32
[0.800]
2.54
[0.100]
1
R0.51
[R0.020]
7
Suggested Pad Layout
21.59
[0.848]
2.54
[0.100]
14
8
14
KEEP OUT AREA
NO CIRCUITRY
UNDER HERE
1
3.05
[0.120]
1.90
[0.075]
8
BOTTOM VIEW BOARD
1.73
[0.068]
14
1.73
[0.068]
2.54
[0.100]
8
13.72
[0.540]
12.70
[0.500]
TOP VIEW COVER
9.40
[0.369]
1
20.07
[0.790]
7
7
5.10
[0.201]
Figure 5.
Figure 6.
Table 3. Absolute Maximum Ratings
Parameter
Power Supply
Output Current
Storage Temperature
Soldering Temp/Time
Symbol
V
CC
I
OUT
TS
T
LS
Ratings
0 to 6
-55 to 125
260/40
Unit
V
mA
°C
°C/sec
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is
not implied at these or any other conditions in excess of conditions represented in the operational sections of this
data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability.
Reliability
VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR
reflow simulation. The FX-424 family is undergoing the following qualification tests:
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
eliability
Handling Precautions
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 4 of 9
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 08Dec06
FX-424 Low Jitter Frequency Translator
Although ESD protection circuitry has been designed into the FX-424 proper precautions should be taken when
handling and mounting. VI employs a human body model (HBM) and a charged-device model (CDM) for ESD
susceptibility testing and design protection evaluation
ESD Ratings
Model
Human Body Model
Charged Device Model
Minimum
500 V
500 V
Conditions
MIL-STD 883, Method 3015
JEDEC, JESD22-C101
Reflow Profile (IPC/JEDEC J-STD-020C)
Parameter
Symbol
PreHeat Time
Ramp Up
Time Above 217
o
C
Time To Peak Temperature
Time At 260
o
C
Ramp Down
t
S
R
UP
t
L
t
AMB-P
t
P
R
DN
Value
60 sec Min, 180 sec Max
3
o
C/sec Max
60 sec Min, 150 sec Max
480 sec Max
20 sec Min, 40 sec Max
6
o
C/sec Max
Temperature (DegC)
The FX-424 is being qualified to meet the JEDEC
standard for Pb-Free assembly. The temperatures
and time intervals listed are based on the Pb-Free
small body requirements. The temperatures refer to
the topside of the package, measured on the package
body surface. The FX-424 should not be subjected to
a wash process that will immerse it in solvents. NO
.CLEAN is the recommended procedure. The FX-424
has been designed for pick and place reflow
soldering. The FX-424 may be reflowed once and
should not be reflowed in the inverted position.
260
t
L
R
t
P
R
DN
t
S
t
AMB-P
217
200
150
25
Time (sec)
Vectron International, 267 Lowell Road, Hudson, NH 03051
Page 5 of 9
Tel: 1-88-VECTRON-1
•
Web:
www.vectron.com
Rev: 08Dec06
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