IS65C256AL
IS62C256AL
32K x 8 LOW POWER CMOS STATIC RAM
ISSI
MARCH 2006
®
FEATURES
• Access time: 25 ns, 45 ns
• Low active power: 200 mW (typical)
• Low standby power
— 150 µW (typical) CMOS standby
— 15 mW (typical) operating
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V power supply
• Lead-free available
• Industrial and Automotive temperatures avail-
able
DESCRIPTION
The
ISSI
IS62C256AL/IS65C256AL is a low power,
32,768 word by 8-bit CMOS static RAM. It is fabricated
using
ISSI
's high-performance, low power CMOS tech-
nology.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) at CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Select (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62C256AL/IS65C256AL is pin compatible with
other 32Kx8 SRAMs in plastic SOP or TSOP (Type I)
package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K X 8
MEMORY ARRAY
VDD
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. A
03/17/06
1
IS65C256AL
IS62C256AL
PIN CONFIGURATION
28-Pin SOP
ISSI
PIN CONFIGURATION
28-Pin TSOP
OE
A11
A9
A8
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
®
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A14
CE
OE
WE
I/O0-I/O7
V
DD
GND
Address Inputs
Chip Select Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
V
DD
Current
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
Unit
V
°C
W
mA
0.5
20
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
IS65C256AL
IS62C256AL
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
CC
1
Parameter
V
DD
Operating
Supply Current
V
DD
Dynamic Operating
Supply Current
Test Conditions
V
DD
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = 0
V
DD
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
-25 ns
Min. Max.
—
15
—
20
—
25
—
—
—
15
—
—
—
—
—
—
5
100
120
150
15
20
50
—
—
—
—
—
—
5
25
30
35
ISSI
Com.
Ind.
Auto.
Com.
Ind.
Auto.
typ.
(2)
Com.
Ind.
Auto.
Com.
Ind.
Auto.
typ.
(2)
-45 ns
Min. Max.
—
15
—
20
—
25
—
—
—
12
100
120
150
15
20
50
µA
20
25
30
Unit
mA
®
I
CC
2
mA
I
SB
1
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
V
DD
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
DD
= Max.,
CE
≥
V
DD
– 0.2V,
V
IN
≥
V
DD
– 0.2V, or
V
IN
≤
0.2V, f = 0
I
SB
2
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
DD
= 5.0V, T
A
= 25
o
C and not 100% tested.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
10
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, V
DD
= 5.0V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
IS65C256AL
IS62C256AL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to Low-Z Output
OE
to High-Z Output
CE
to Low-Z Output
CE
to High-Z Output
CE
to Power-Up
CE
to Power-Down
-25 ns
Min. Max.
25
—
2
—
—
0
0
3
0
0
—
—
25
—
25
13
—
12
—
12
—
20
-45 ns
Min.
Max.
45
—
2
—
—
0
0
3
0
0
—
—
45
—
45
25
—
20
—
20
—
30
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCS
(2)
t
HZCS
(2)
t
PU
(3)
t
PD
(3)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480
Ω
5V
5V
480
Ω
OUTPUT
100 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
5
PCB Design
京公网安备 11010802033920号
EEWORLD
