3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
256 x 9-bit organization IDT72V201
512 x 9-bit organization IDT72V211
1,024 x 9-bit organization IDT72V221
2,048 x 9-bit organization IDT72V231
4,096 x 9-bit organization IDT72V241
8,192 x 9-bit organization IDT72V251
10 ns read/write cycle time
5V input tolerant
Read and Write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set to
any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output Enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
°
°
DESCRIPTION:
The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. The architecture, functional operation and pin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks and interprocessor
communication.
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every rising
clock edge when the Write Enable pins are asserted. The output port is
controlled by another clock pin (RCLK) and two Read Enable pins (REN1,
REN2).
The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dual-
clock operation. An Output Enable pin (OE) is provided on the read port
for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for
PAE
and
PAF,
respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the Load pin (LD).
These FIFOs are fabricated using IDT's high-speed submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
INPUT REGISTER
OFFSET REGISTER
EF
PAE
PAF
FF
D
0
- D
8
LD
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
Q
0
- Q
8
4092 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2002
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2002
DSC-4092/2
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATION
RS
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
2
D
3
D
4
D
5
D
6
D
7
INDEX
INDEX
32 31 30 29 28 27 26 25
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
4
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
14 15 16 17 18 19 20
EF
FF
Q
0
Q
1
Q
2
Q
3
OE
EF
Q
0
Q
1
Q
2
Q
3
FF
Q
4
Q
4
4092 drw02
D
8
4092 drw02a
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PIN DESCRIPTIONS
Symbol
D
0
-D
8
RS
WCLK
WEN1
WEN2/
LD
Q
0
-Q
8
RCLK
REN1
REN2
OE
EF
PAE
PAF
FF
V
CC
GND
I/O
Description
I Data inputs for a 9-bit bus.
I When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A Reset is required before an initial Write after power-up.
Write Clock
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
Write Enable 1
I If the FIFO is configured to have programmable flags,
WEN1
is the only Write Enable pin. When
WEN1
is
LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to
have two write enables,
WEN1
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data
will not be written into the FIFO if the
FF
is LOW.
Write Enable 2/
I The FIFO is configured at Reset to have either two write enables or programmable flags. If WEN2/
LD
Load
is HIGH at Reset, this pin operates as a second write enable. If WEN2/
LD
is LOW at Reset, this pin operates
as a control to load and read the programmable flag offsets. If the FIFO is configured to have two write
enables,
WEN1
must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written
into the FIFO if the
FF
is LOW. If the FIFO is configured to have programmable flags, WEN2/
LD
is held LOW to
write or read the programmable flag offsets.
Data Outputs
O Data outputs for a 9-bit bus.
Read Clock
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN1
and
REN2
are asserted.
Read Enable 1
I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data
will not be read from the FIFO if the
EF
is LOW.
Read Enable 2
I When
REN1
and
REN2
are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
Output Enable
I When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
Empty Flag
O When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is
HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
Programmable
O When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
Almost-Empty Flag
offset at reset is Empty+7.
PAE
is synchronized to RCLK.
Programmable
O When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default
Almost-Full Flag
offset at reset is Full-7.
PAF
is synchronized to WCLK.
Full Flag
O When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO
is not full.
FF
is synchronized to WCLK.
Power
One 3.3V volt power supply pin.
Ground
One 0 volt ground pin.
2
Name
Data Inputs
Reset
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
Com'l & Ind'l
–0.5 to +5
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
T
A
T
A
Parameter
Supply Voltage
Commercial/Industrial
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
3.0
0
2.0
-0.5
0
-40
Typ.
3.3
0
—
—
—
—
Max.
3.6
0
5.5
0.8
70
85
Unit
V
V
V
V
°C
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminal only.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 3.3V ± 0.3V, T
A
= 0°C to +70°C;Industrial: V
CC
= 3.3V ± 0.3V, T
A
= -40°C to +85°C)
IDT72V201
IDT72V211
IDT72V221
IDT72V231
IDT72V241
IDT72V251
Commercial and Industrial
(1)
t
CLK
= 10, 15, 20 ns
Typ.
—
—
—
—
—
—
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4,7)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2mA
Output Logic “0” Voltage, I
OL
= 8mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
20
5
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4
≤
VIN
≤
VCC.
3.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
4. Tested with outputs disabled (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical I
CC1
= 0.17 + 0.48*f
S
+ 0.02*C
L
*f
S
(in mA) with V
CC
= 3.3V, T
A
= 25
°
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2,
C
L
= capacitive load (in pF).
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected (OE
≥
V
IH
).
2. Characterized values, not currently tested.
3
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: V
CC
= 3.3 ±0.3V, TA = 0°C to + 70°C;Industrial: V
CC
= 3.3 ±0.3V, TA = -40°C to + 85°C)
Commercial
IDT72V201L10
IDT72V211L10
IDT72V221L10
IDT72V231L10
IDT72V241L10
IDT72V251L10
Min.
Max.
—
100
2
10
4.5
4.5
3
0.5
3
0.5
10
8
8
—
0
3
3
—
—
—
—
5
14
6.5
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6.5
6.5
6.5
6.5
—
—
Com'l & Ind'l
(2)
IDT72V201L15
IDT72V211L15
IDT72V221L15
IDT72V231L15
IDT72V241L15
IDT72V251L15
Min.
Max.
—
66.7
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
—
—
6
18
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
10
10
—
—
Commercial
IDT72V201L20
IDT72V211L20
IDT72V221L20
IDT72V231L20
IDT72V241L20
IDT72V251L20
Min.
Max.
—
50
2
20
8
8
5
1
5
1
20
12
12
—
0
3
3
—
—
—
—
8
20
12
—
—
—
—
—
—
—
—
—
—
20
—
10
10
12
12
12
12
—
—
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
AF
t
AE
t
SKEW1
t
SKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
(3)
Output Enable to Output Valid
Output Enable to Output in High-Z
(3)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Skew time between Read Clock & Write
Clock for Empty Flag &Full Flag
Skew time between Read Clock & Write
Clock for Almost-Empty Flag &
Almost-Full Flag
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Industrial temperature range is available by special order for speed grades faster than 15ns.
3. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
510Ω
30pF*
4092 drw03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
4
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
WRITE ENABLE 2/LOAD (WEN2/LD)
This is a dual-purpose pin. The FIFO is configured at Reset to have
programmable flags or to have two write enables, which allows depth expansion.
If Write Enable 2/Load (WEN2/LD) is set high at Reset (RS = LOW), this pin
operates as a second Write Enable pin.
If the FIFO is configured to have two write enables, when Write Enable
(WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock (WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable (WEN1) is HIGH and/or Write
Enable 2/Load (WEN2/LD) is LOW, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
WFF
, allowing a valid write to begin. Write Enable 1 (WEN1)
and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when the Write Enable
2/Load (WEN2/LD) is set LOW at Reset (RS = LOW). The IDT72V201/72V211/
72V221/72V231/72V241/72V251 devices contain four 8-bit offset registers
which can be loaded with data on the inputs, or read on the outputs. See Figure
3 for details of the size of the registers and the default values.
If the FIFO is configured to have programmable flags when the Write Enable
1 (WEN1) and Write Enable 2/Load (WEN2/LD) are set low, data on the inputs
D is written into the Empty (Least Significant Bit) Offset register on the first LOW-
to-HIGH transition of the Write Clock (WCLK). Data is written into the Empty (Most
Significant Bit) Offset register on the second LOW-to-HIGH transition of the Write
Clock (WCLK), into the Full (Least Significant Bit) Offset register on the third
transition, and into the Full (Most Significant Bit) Offset register on the fourth
transition. The fifth transition of the Write Clock (WCLK) again writes to the Empty
(Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the Write Enable 2/
Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write
operation. When the Write Enable 2/Load (WEN2/LD) pin is set LOW, and Write
Enable 1 (WEN1) is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output lines when the
Write Enable 2/Load (WEN2/LD) pin is set low and both Read Enables (REN1,
REN2)
are set LOW. Data can be read on the LOW-to-HIGH transition of the
Read Clock (RCLK).
A read and write should not be performed simultaneously to the offset
registers.
LD
0
WEN1
0
WCLK
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (FF) and Programmable Almost-Full Flag (PAF) will be reset to HIGH
after t
RSF
. The Empty Flag (EF) and Programmable Almost-Empty Flag (PAE)
will be reset to LOW after t
RSF
. During reset, the output register is initialized to
all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the Write Clock (WCLK). The Full Flag (FF) and Programmable
Almost-Full Flag (PAF) are synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
The Write and Read clocks can be asynchronous or coincident.
WRITE ENABLE 1 (WEN1)
If the FIFO is configured for programmable flags, Write Enable 1 (WEN1)
is the only enable control pin. In this configuration, when Write Enable 1 (WEN1)
is low, data can be loaded into the input register and RAM array on the LOW-
to-HIGH transition of every Write Clock (WCLK). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion, there are two enable control pins. See Write Enable 2 paragraph
below for operation in this configuration.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (FF)
will go HIGH after t
WFF
, allowing a valid write to begin. Write Enable 1 (WEN1)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (EF) and Programmable Almost-Empty Flag
(PAE) are synchronized with respect to the LOW-to-HIGH transition of the Read
Clock (RCLK).
The Write and Read clocks can be asynchronous or coincident.
READ ENABLES (REN1,
REN2)
When both Read Enables (REN1,
REN2)
are LOW, data is read from the
RAM array to the output register on the LOW-to-HIGH transition of the Read
Clock (RCLK).
When either Read Enable (REN1,
REN2)
is HIGH, the output register holds
the previous data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (EF) will go
LOW, inhibiting further read operations. Once a valid write operation has been
accomplished, the Empty Flag (EF) will go HIGH after t
REF
and a valid read can
begin. The Read Enables (REN1,
REN2)
are ignored when the FIFO is empty.
5
0
1
1
1
0
1
NOTES:
1. For the purposes of this table, WEN2 = V
IH
.
2. The same selection sequence applies to reading from the registers.
REN1
and
REN2
are enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Write Offset Register
FPGA/CPLD
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