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8745BYILF

Description
clock generators & support products 5 lvds out mult/divider
Categorysemiconductor    Other integrated circuit (IC)   
File Size809KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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8745BYILF Overview

clock generators & support products 5 lvds out mult/divider

1:5 Differential-to-LVDS Zero Delay
Clock Generator
ICS8745BI
DATA SHEET
General Description
The ICS8745BI is a highly versatile 1:5 LVDS Clock
Generator and a member of the HiPerClockS™ family
HiPerClockS™
of High Performance Clock Solutions from IDT. The
ICS8745BI has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider,
and has an output frequency range of 31.25MHz to 700MHz. The
Reference Divider, Feedback Divider and Output Divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
Five differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
Selectable differential clock inputs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 30ps (maximum)
Output skew: 40ps (maximum)
Static phase offset: 25ps ± 125ps
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
Q0
nQ0
PLL_SEL
Pullup
Pin Assignment
PLL_SEL
SEL3
V
DDA
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
CLK_SEL
Pulldown
FB_IN
Pulldown
nFB_IN
Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32
,
÷64
0
Q1
nQ1
0
Q2
nQ2
Q3
nQ3
Q4
nQ4
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
Q3
nQ3
V
DDO
Q2
nQ2
GND
Q1
nQ1
1
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
nFB_IN
FB_IN
SEL2
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
ICS8745BI
32-Lead LQFP 7mm x 7mm x 1.4mm
package body
Top View
ICS8745BYI REVISION D JUNE 11, 2009
1
©2009 Integrated Device Technology, Inc.
GND
V
DDO
nQ0
V
DD
Q0
GND
V
DDO
Q4
nQ4
V
DD

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