PCA9515
I
2
C-bus repeater
Rev. 09 — 23 April 2009
Product data sheet
1. General description
The PCA9515 is a BiCMOS integrated circuit intended for application in I
2
C-bus and
SMBus systems.
While retaining all the operating modes and features of the I
2
C-bus system, it permits
extension of the I
2
C-bus by buffering both the data (SDAn) and the clock (SCLn) lines,
thus enabling two buses of 400 pF.
The I
2
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515 enables the system designer to isolate two halves of a bus, thus more
devices or longer length can be accommodated. It can also be used to run two buses, one
at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is
isolated when 400 kHz operation of the other is required.
Two or more
PCA9515s
cannot be put in series.
The PCA9515 design does not allow
this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage levels
are used to avoid lock-up conditions between the input and the output. A ‘regular low’
applied at the input of a PCA9515 will be propagated as a ‘buffered low’ with a slightly
higher value. When this ‘buffered low’ is applied to another PCA9515, PCA9516A, or
PCA9518A in series, the second PCA9515, PCA9516A, or PCA9518A will not recognize
it as a ‘regular low’ and will not propagate it as a ‘buffered low’ again. The
PCA9510A/9511A/9513A/9514A and PCA9512A cannot be used in series with the
PCA9515, PCA9516A, or PCA9518A but can be used in series with themselves since
they use shifting instead of static offsets to avoid lock-up conditions.
The PCA9515 SCLn/SDAn C
i
is about 200 pF versus the normal < 10 pF when V
CC
= 0 V.
The newer PCA9515A should be used in applications where power is secured to the
repeater but an active bus remains on either set of SCLn/SDAn pins to prevent this
increase in bus loading. Additionally, the PCA9515A has a wider voltage range of 2.3 V to
3.6 V and can be used in applications with lower voltage supply constraints.
2. Features
I
I
I
I
I
I
I
I
I
2 channel, bidirectional buffer
I
2
C-bus and SMBus compatible
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
Powered-off high-impedance I
2
C-bus pins
Operating supply voltage range of 3.0 V to 3.6 V
NXP Semiconductors
PCA9515
I
2
C-bus repeater
I
5.5 V tolerant I
2
C-bus (SCLn, SDAn) and enable (EN) pins
I
0 Hz to 400 kHz clock frequency
1
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
Packages offered: SO8 and TSSOP8 (MSOP8)
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA9515D
PCA9515DP
[1]
Type number
Description
plastic small outline package; 8 leads;
body width 3.9 mm
plastic thin shrink small outline package; 8 leads;
body width 3 mm
Version
SOT96-1
SOT505-1
SO8
TSSOP8
[1]
Also known as MSOP8.
3.1 Ordering options
Table 2.
PCA9515D
PCA9515DP
Ordering options
Topside mark
PCA9515
9515
Temperature range
T
amb
=
−40 °C
to +85
°C
T
amb
=
−40 °C
to +85
°C
Type number
4. Block diagram
V
CC
PCA9515
SDA0
SDA1
SCL0
pull-up
resistor
EN
002aae620
SCL1
GND
Fig 1.
Block diagram of PCA9515
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
1.
The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
© NXP B.V. 2009. All rights reserved.
PCA9515_9
Product data sheet
Rev. 09 — 23 April 2009
2 of 16
NXP Semiconductors
PCA9515
I
2
C-bus repeater
5. Pinning information
5.1 Pinning
n.c.
SCL0
SDA0
GND
1
2
8
7
V
CC
SCL1
SDA1
EN
n.c.
SCL0
SDA0
GND
1
2
3
4
002aac744
8
7
V
CC
SCL1
SDA1
EN
PCA9515D
3
4
002aac743
6
5
PCA9515DP
6
5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for TSSOP8
5.2 Pin description
Table 3.
Symbol
n.c.
SCL0
SDA0
GND
EN
SDA1
SCL1
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
not connected
serial clock bus 0
serial data bus 0
supply ground
active HIGH repeater enable input
serial data bus 1
serial clock bus 1
supply power
PCA9515_9
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 09 — 23 April 2009
3 of 16
NXP Semiconductors
PCA9515
I
2
C-bus repeater
6. Functional description
The PCA9515 BiCMOS integrated circuit contains two identical buffer circuits which
enable I
2
C-bus and similar bus systems to be extended without degradation of system
performance. (Refer to
Figure 1 “Block diagram of PCA9515”.)
The PCA9515 BiCMOS integrated circuit contains two bidirectional open-drain buffers
specifically designed to support the standard low-level-contention arbitration of the
I
2
C-bus. Except during arbitration or clock stretching, the PCA9515 acts like a pair of
non-inverting, open-drain buffers, one for SDA and one for SCL.
6.1 Enable
The EN pin is active HIGH with an internal pull-up and allows the user to select when the
repeater is active. This can be used to isolate a badly behaved slave on power-up until
after the system power-up reset. It should never change state during an I
2
C-bus operation
because disabling during a bus operation will hang the bus and enabling part way through
a bus cycle could confuse the I
2
C-bus parts being enabled.
The enable pin (EN) should only change state when the global bus and the repeater port
are in an idle state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector configuration of the I
2
C-bus.)
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part is designed to work with Standard-mode and
Fast-mode I
2
C-bus devices in addition to SMBus devices. Standard-mode I
2
C-bus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic
I
2
C-bus system where Standard-mode devices and multiple masters are possible. Under
certain conditions, higher termination currents can be used. Please see application note
AN255, “I
2
C/SMBus Repeaters, Hubs and Expanders”
for additional information on sizing
resistors and precautions when using more than one PCA9515 in a system or using the
PCA9515 in conjunction with the P82B96.
PCA9515_9
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 09 — 23 April 2009
4 of 16
NXP Semiconductors
PCA9515
I
2
C-bus repeater
7. Application design-in information
A typical application is shown in
Figure 4.
In this example, the system master is running
on a 3.3 V I
2
C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
3.3 V
5V
V
CC
SDA
SCL
BUS
MASTER
400 kHz
SDA0
SCL0
SDA1
SCL1
SDA
SCL
SLAVE
100 kHz
PCA9515
EN
bus 0
bus 1
002aae621
Fig 4.
Typical application
The PCA9515 is 5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9515 is pulled LOW by a device on the I
2
C-bus, a CMOS
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9515 will typically be at V
OL
= 0.5 V.
In order to illustrate what would be seen in a typical application, refer to
Figure 5
and
Figure 6.
If the bus master in
Figure 4
were to write to the slave through the PCA9515, we
would see the waveform shown in
Figure 5
on Bus 0. This looks like a normal I
2
C-bus
transmission until the falling edge of the 8
th
clock pulse. At that point, the master releases
the data line (SDA) while the slave pulls it LOW through the PCA9515. Because the V
OL
of
the PCA9515 is typically around 0.5 V, a step in the SDA will be seen. After the master
has transmitted the 9
th
clock pulse, the slave releases the data line.
On the Bus 1 side of the PCA9515, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9515. After the 8
th
clock pulse, the data line will
be pulled to the V
OL
of the slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the V
OL
of the devices on Bus 1 be 70 mV below the V
OL
of the PCA9515 (see V
OL
−V
ILc
in
Section 9 “Static characteristics”)
to be recognized by the PCA9515 and then transmitted
to Bus 0.
PCA9515_9
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 09 — 23 April 2009
5 of 16
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