NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes effect of voltage output DAC, voltage references.
(4) Guaranteed but not tested.
PIN DESIGNATIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DESCRIPTOR
V
OUT
B
V
OUT
A
–V
REF
Out
V
REF
In
+V
REF
Out
BPO
–V
S
+V
S
AGND
DGND
+V
L
V
OUT
D
V
OUT
C
CLR
FUNCTION
Analog output voltage, DAC B
Analog output voltage, DAC A
Negative reference voltage output (–10V output)
±
Reference voltage input
Positive reference voltage output (+10V output)
Bipolar offset input, DAC A, B, C, and D
Negative analog power supply, –15V input
Positive analog power supply, +15V input
Analog common
Digital common
Positive logic power supply, +5V input
Analog output voltage, DAC D
Analog output voltage, DAC C
Asynchronous input reset to zero
PIN
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DESCRIPTOR
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
LE
CS
WR
FUNCTION
Address line 2 input
Address line 1 input
Address line 0 input
Data bit 7 input
Data bit 6 input
Data bit 5 input
Data bit 4 input
Data bit 3 input
Data bit 2 input
Data bit 1 input
Data bit 0 input
Latch data enable, DAC A, B, C, and D
Chip select enable, DAC A, B, C, and D
Write input, DAC A, B, C, and D
PIN CONFIGURATIONS
Top View
ABSOLUTE MAXIMUM RATINGS
28 A
2
27 A
1
26 A
0
25 D
7
24 D
6
23 D
5
+V
L
to AGND ................................................................................. 0V, +7V
+V
L
to DGND ................................................................................ 0V, +7V
+V
S
to AGND .............................................................................. 0V, +18V
–V
S
to AGND ............................................................................... 0V,–18V
AGND to DGND ................................................................................
±0.3V
Any digital input to GND ................................................. –0.3V, +V
L
+0.3V
Ref In to AGND ..................................................................................
±25V
Ref In to DGND ..................................................................................
±25V
Storage Temperature Range .......................................... –55°C to +125°C
Operating Temperature Range ......................................... –40°C to +85°C
Lead Temperature (soldering, 10s) ................................................ +300°C
Junction Temperature .................................................................... +155°C
Output Short Circuit ................................... Continuous to common or
±V
S
Reference Short Circuit .............................. Continuous to common or +V
S
V
OUT
B
V
OUT
A
–V
REF
Out
V
REF
In
+V
REF
Out
BPO
–V
S
+V
S
AGND
DGND
+V
L
V
OUT
D
V
OUT
C
CLR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DAC4815
22 D
4
21 D
3
20 D
2
19 D
1
18 D
0
17 LE
16 CS
15 WR
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.
PACKAGE INFORMATION
100+
$24.95
29.95
MODEL
DAC4815AP
DAC4815BP
PACKAGE
28-Pin Plastic DIP
28-PIn Plastic DIP
PACKAGE DRAWING
NUMBER
(1)
215
215
ORDERING INFORMATION
ORDERING INFORMATION
MODEL
MODEL
DAC4815AP
DAC4815AP
DAC4815BP
DAC4815BP
1–24
$35.85
43.05
USA OEM PRICES
LINEARITY ERROR
25–99
(LSB)
$28.45
±1
34.15
±1/2
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
®
3
DAC4815
TYPICAL PERFORMANCE CURVES
T
A
= +25°C, V
S
=
±12V
or
±15V,
V
L
= +5V unless otherwise noted.
PSRR vs FREQUENCY (Bipolar Mode)
80
NOISE vs BANDWIDTH (Bipolar Mode)
250
Voltage Noise (µVrms)
70
60
200
PSRR (dB)
50
40
30
20
10
0
1k
10k
100k
Frequency (Hz)
1M
V
OUT
= +10V
V
OUT
= 0V
150
V
OUT
= +10V
FFF
HEX
100
50
V
OUT
= 0V
800
HEX
0
100
1k
10k
Frequency (Hz)
100k
1M
CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR
vs TEMPERATURE
POWER SUPPLY CURRENT vs TEMPERATURE
∆
Bipolar Offset and Zero Error (mV)
1.5E+00
1.0E+00
5.0E+00
0.0E+00
–5.0E–01
–1.0E+00
–1.5E+00
–40
–20
0
20
40
60
+80
100
Temperature (°C)
Bipolar Offset
Bipolar Zero
Gain Error
1.5E–02
1.0E–02
21.8
21.5
+I
L
(All Logic Inputs = 2V)
7
6
5
±I
S
(mA) Analog Supply
∆
Gain Error (%)
21.2
20.9
20.6
20.3
20
19.4
–40
–20
0
20
40
60
80
Temperature (°C)
+I
L
(All Logic Inputs = 0V or V
L
)
I
S
5.0E–03
0.0E+00
–5.0E–03
–1.0E–02
–1.5E–02
4
3
2
1
0
OUTPUT VOLTAGE SWING vs RESISTOR LOAD
25
CROSSTALK (Bipolar Mode)
20
V
OUT
(Vp-p)
V
S
= ±15V
V
L
= 5V
10V REF
0V
V
OUT
B
15
V
OUT
10
+5V
V
OUT
A
LE
5
0V
0
10
100
1k
10k
Load Resistance (
Ω
)
Time (500ns/div)
NOTE: Crosstalk is dominated by digital crosstalk/
feedthrough of LE signal.
®
DAC4815
4
+I
L
(mA) Logic Supply
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25°C, V
S
=
±12V
or
±15V,
V
L
= +5V unless otherwise noted.
FULL-SCALE OUTPUT SWING
BIPOLAR (20V Step)
SETTLING TIME
BIPOLAR (–10V to +10V)
0V
V
OUT
∆V
Around +10V (2mV/div)
V
OUT
(5V/div)
+10V
+5V
0V
V
OUT
LE
+5V
0V
LE
Time (2µs/div)
Time (1µs/div)
SETTLING TIME
BIPOLAR (+10V to –10V Step)
MAJOR CARRY GLITCH
∆V
Around –10V (2mV/div)
–10V
V
OUT
V
OUT
(20mV/div)
0V
V
OUT
+5V
0V
LE
0V
+5V
0V
LE
Time (2µs/div)
Time (1µs/div)
NOTE: Data transition 800
HEX
to 7FF
HEX
.
DIGITAL FEEDTHROUGH
V
OUT
(5mV/div)
0V
V
OUT
Time (500ns/div)
DAC output noise due to activity on digital inputs
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