PPC440GP-3FC500CZ datasheet, PDF

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PPC440GP-3FC500CZ: DescriptionRISC Microprocessor, 32-Bit, 500MHz, CMOS, PBGA552, 25 X 25 MM, FLIP CHIP, PLASTIC, BGA-552; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，68 Pages; ManufacturerApplied Micro Circuits (MACOM)

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PPC440GP-3FC500CZ Overview

RISC Microprocessor, 32-Bit, 500MHz, CMOS, PBGA552, 25 X 25 MM, FLIP CHIP, PLASTIC, BGA-552

PPC440GP-3FC500CZ Parametric

Parameter Name	Attribute value
Maker	Applied Micro Circuits (MACOM)
Parts packaging code	BGA
package instruction	BGA,
Contacts	552
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	ALSO REQUIRES 3.3V SUPPLY
Address bus width	64
bit size	32
boundary scan	YES
maximum clock frequency	66.66 MHz
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B552
length	25 mm
low power mode	YES
Number of terminals	552
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.361 mm
speed	500 MHz
Maximum supply voltage	1.9 V
Minimum supply voltage	1.7 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC
Base Number Matches	1

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Confidential & Proprietary

PRELIMINARY MATERIAL

Part Number 440GP

Revision 1.01 – July 30, 2004

440GP

PowerPC 440GP Embedded Processor

FEATURES

•

PowerPC

440 processor core operating up to

500MHz with 32KB I- and D-caches

On-chip 8 KB SRAM

Selectable processor:bus clock ratios of 3:1,

4:1, 5:1, 5:2, 7:2

Double Data Rate (DDR) Synchronous DRAM

(SDRAM) 32/64-bit interface operating up to

133MHz

External Peripheral Bus for up to eight devices

with external mastering

DMA support for external peripherals, internal

UART and memory

PCI-X V1.0a interface (32 or 64 bits, up to

133MHz) with support for conventional PCI

V2.2

Two Ethernet 10/100Mbps half- or full-duplex

interfaces. Operational modes supported are

MII, RMII, and SMII.

Programmable Interrupt Controller supports

interrupts from a variety of sources.

Programmable General Purpose Timers (GPT)

Two serial ports (16750 compatible UART)

Two IIC interfaces

General Purpose I/O (GPIO) interface avail-

able

JTAG interface for board level testing

Internal Processor Local Bus (PLB) runs at

DDR SDRAM interface frequency

Processor can boot from PCI memory

Available in ceramic and plastic packages

Preliminary Data Sheet

DESCRIPTION

Designed specifically to address high-end embedded

applications, the PowerPC 440GX (PPC440GX) pro-

vides a high-performance, low power solution that

interfaces to a wide range of peripherals by incorporat-

ing on-chip power management features and lower

power dissipation.

This chip contains a high-performance RISC processor

core, DDR SDRAM controller,8KB SRAM, PCI-X bus

interface, Ethernet interfaces, control for external ROM

and peripherals, DMA with scatter-gather support, serial

ports, IIC interface, and general purpose I/O.

Technology: CMOS SA-27E, 0.18

µm

(0.11 L

eff

), 5-

layer metal

Packages: 25 mm, 552-ball Ceramic Ball Grid Array

(CBGA) or Plastic Ball Grid Array (PBGA)

Power (estimated): Less than:

4.0W in normal mode

1.0 W in sleep mode

Supply voltages required: 3.3V, 2.5V, 1.8V

•

AMCC Confidential and Proprietary

440GP – PowerPC 440GP Embedded Processor

Revision 1.01 – July 30, 2004

Preliminary Data Sheet

TABLE OF CONTENTS

FEATURES .............................................................................................................................................................. 1

DESCRIPTION ........................................................................................................................................................ 1

ORDERING AND PVR INFORMATION .................................................................................................................. 4

Order Part Number Key ..................................................................................................................................... 4

ADDRESS MAPS .................................................................................................................................................... 5

POWERPC 440 PROCESSOR CORE .................................................................................................................... 8

INTERNAL BUSES ................................................................................................................................................. 8

ON-CHIP SRAM ...................................................................................................................................................... 9

PCI-X INTERFACE .................................................................................................................................................. 9

DDR SDRAM MEMORY CONTROLLER .............................................................................................................. 10

EXTERNAL PERIPHERAL BUS CONTROLLER (EBC) ...................................................................................... 10

ETHERNET CONTROLLER INTERFACE ............................................................................................................ 11

DMA CONTROLLER ............................................................................................................................................. 11

SERIAL PORT ....................................................................................................................................................... 11

IIC BUS INTERFACE ............................................................................................................................................ 11

GENERAL PURPOSE TIMERS (GPT) .................................................................................................................. 12

GENERAL PURPOSE IO (GPIO) CONTROLLER ................................................................................................ 12

UNIVERSAL INTERRUPT CONTROLLER (UIC) ................................................................................................. 12

JTAG ..................................................................................................................................................................... 12

SIGNAL LISTS ...................................................................................................................................................... 15

SIGNAL DESCRIPTION ........................................................................................................................................ 38

Multiplexed Signals .......................................................................................................................................... 38

Multipurpose Signals ....................................................................................................................................... 38

Multimode Signals ........................................................................................................................................... 38

Strapping Pins ................................................................................................................................................. 38

HEAT SINK MOUNTING INFORMATION (CERAMIC PACKAGE ONLY) ........................................................... 46

TEST CONDITIONS .............................................................................................................................................. 48

SPREAD SPECTRUM CLOCKING ....................................................................................................................... 50

DDR SDRAM I/O SPECIFICATIONS .................................................................................................................... 57

DDR SDRAM WRITE OPERATION ...................................................................................................................... 59

DDR SDRAM READ OPERATION ........................................................................................................................ 61

INITIALIZATION .................................................................................................................................................... 66

STRAPPING .......................................................................................................................................................... 66

EEPROM ............................................................................................................................................................... 66

DOCUMENT REVISION HISTORY ....................................................................................................................... 67

AMCC Confidential and Proprietary

440GP – PowerPC 440GP Embedded Processor

Revision 1.01 – July 30, 2004

Preliminary Data Sheet

LIST OF FIGURES

Figure 1. PPC440GX Functional Block Diagram ..................................................................................................... 5

Figure 2. 25mm, 552-Ball CBGA Package ............................................................................................................ 13

Figure 3. 25mm, 552-Ball FC-PBGA Package ...................................................................................................... 14

Figure 4. Heat Sink Attached With Spring Clip ...................................................................................................... 46

Figure 5. Heat Sink Attached With Adhesive ......................................................................................................... 46

Figure 6. Timing Waveform .................................................................................................................................... 49

Figure 7. Input Setup and Hold Waveform ............................................................................................................. 52

Figure 8. Output Delay and Float Timing Waveform .............................................................................................. 52

Figure 9. DDR SDRAM Signal Termination ........................................................................................................... 58

Figure 10. DDR SDRAM Write Cycle Timing ......................................................................................................... 59

Figure 11. DDR SDRAM MemClkOut0 and Read Clock Delay ............................................................................. 61

Figure 12. DDR SDRAM Read Data Path ............................................................................................................. 62

Figure 13. DDR SDRAM Read Cycle Timing—Example 1 .................................................................................... 63

Figure 14. DDR SDRAM Read Cycle Timing—Example 2 .................................................................................... 64

Figure 15. DDR SDRAM Read Cycle Timing—Example 3 .................................................................................... 65

LIST OF TABLES

Table 1. System Memory Address Map ................................................................................................................... 6

Table 2. DCR Address Map 4KB of Device Configuration Registers ....................................................................... 7

Table 3. Signals Listed Alphabetically ................................................................................................................... 15

Table 4. Signals Listed by Ball Assignment ........................................................................................................... 32

Table 5. Pin Summary ........................................................................................................................................... 38

Table 6. Signal Functional Description .................................................................................................................. 39

Table 7. Absolute Maximum Ratings ..................................................................................................................... 45

Table 8. Package Thermal Specifications .............................................................................................................. 45

Table 9. Recommended DC Operating Conditions ................................................................................................ 47

Table 10. Input Capacitance .................................................................................................................................. 48

Table 11. DC Power Supply Loads ........................................................................................................................ 48

Table 12. Clocking Specifications .......................................................................................................................... 49

Table 13. Peripheral Interface Clock Timings ........................................................................................................ 51

Table 14. I/O Specifications—All Speeds .............................................................................................................. 53

Table 15. I/O Specifications—400, 466, and 500MHz ........................................................................................... 56

Table 16. DDR SDRAM Output Driver Specifications ............................................................................................ 58

Table 17. I/O Timing—DDR SDRAM T

.............................................................................................................. 60

Table 18. I/O Timing—DDR SDRAM T

, T

, and T

....................................................................................... 60

Table 19. I/O Timing—DDR SDRAM T

and T

................................................................................................ 61

Table 20. I/O Timing—DDR SDRAM T

SIN

and T

DIN

.............................................................................................. 62

Table 21. Strapping Pin Assignments .................................................................................................................... 66

AMCC Confidential and Proprietary

PPC440GP-3FC500CZ Related Products

	PPC440GP-3FC500CZ	PPC440GP-3FC500C	PPC440GP-3FC466CZ
Description	RISC Microprocessor, 32-Bit, 500MHz, CMOS, PBGA552, 25 X 25 MM, FLIP CHIP, PLASTIC, BGA-552	RISC Microprocessor, 32-Bit, 500MHz, CMOS, PBGA552, 25 X 25 MM, FLIP CHIP, PLASTIC, BGA-552	RISC Microprocessor, 32-Bit, 466MHz, CMOS, PBGA552, 25 X 25 MM, FLIP CHIP, PLASTIC, BGA-552
Maker	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)	Applied Micro Circuits (MACOM)
Parts packaging code	BGA	BGA	BGA
package instruction	BGA,	BGA,	BGA,
Contacts	552	552	552
Reach Compliance Code	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3
Other features	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY	ALSO REQUIRES 3.3V SUPPLY
Address bus width	64	64	64
bit size	32	32	32
boundary scan	YES	YES	YES
maximum clock frequency	66.66 MHz	66.66 MHz	66.66 MHz
External data bus width	64	64	64
Format	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	YES
JESD-30 code	S-PBGA-B552	S-PBGA-B552	S-PBGA-B552
length	25 mm	25 mm	25 mm
low power mode	YES	YES	YES
Number of terminals	552	552	552
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.361 mm	3.361 mm	3.361 mm
speed	500 MHz	500 MHz	466 MHz
Maximum supply voltage	1.9 V	1.9 V	1.9 V
Minimum supply voltage	1.7 V	1.7 V	1.7 V
Nominal supply voltage	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	25 mm	25 mm	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	1	1	1

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