analog converter. The chip combines a precision volt-
age reference, microcomputer interface logic, and
double-buffered latch, in a 12-bit D/A converter with
a voltage output amplifier. Fast current switches and a
laser-trimmed thin-film resistor network provide a
highly accurate and fast D/A converter.
Microcomputer interfacing is facilitated by a double-
buffered latch. The input latch is divided into three
4-bit nibbles to permit interfacing to 4-, 8-, 12-, or
16-bit buses and to handle right-or left-justified data.
The 12-bit data in the input latches is transferred to the
D/A latch to hold the output value.
4 MSBs
4 LSBs
S
J
Input Latch
Input Latch
Input Latch
R
F
10V
D/A Latch
R
F
V
OUT
BPO
12-Bit D/A Converter
R
BPO
Voltage Reference
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
NOTES: (1) USB = unipolar straight binary; BOB = bipolar offset binary. (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim
potentiometer. (4) Error at input code 000
16
for both unipolar and bipolar ranges. (5) FSR means full scale range and is 20V for the
±10V
range. (6) Maximum
represents the 3σ limit. Not 100% tested for this parameter. (7) At the major carry, 7FF
16
to 800
16
and 800
16
to 7FF
16
. (8) Minimum supply voltage required for
±10V
output swing is
±13.5V.
Output swing for
±11.4V
supplies is at least –8V to +8V. (9) The maximum voltage at which ACOM and DCOM may be separated without
affecting accuracy specifications.
®
DAC811
2
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
+V
DD
WR
LDAC
N
A
N
B
N
C
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
DCOM
D
0
D
1
D
2
D
3
+V
CC
–V
CC
Gain Adj
ACOM
V
OUT
10V Range
SJ
BPO
Ref Out
FUNCTION
Logic supply, +5V.
Write, command signal to load latches. Logic low
loads latches.
Load D/A converter, enables WR to load the D/A
latch. Logic low enables.
Nibble A, enables WR to load input latch A (the
most significant nibble). Logic low enables.
Nibble B, enables WR to load input latch B. Logic
low enables.
Nibble C, enables WR to load input latch C (the
least significant nibble). Logic low enables.
Data bit 12, MSB, positive true.
Data bit 11.
Data bit 10.
Data bit 9.
Data bit 8.
Data bit 7.
Data bit 6.
Data bit 5.
Digital common, V
DD
supply return.
Data bit 1, LSB.
Data bit 2.
Data bit 3.
Data bit 4.
Analog supply input, +15V or +12V.
Analog supply input, –15V or –12V.
To externally adjust gain.
Analog common,
±V
CC
supply return.
D/A converter voltage output.
Connect to pin 24 for 10V range.
Summing junction of output amplifier.
Bipolar offset. Connect to pin 26 for bipolar
operation.
6.3V reference output.
ABSOLUTE MAXIMUM RATINGS
+V
CC ................................................................................................................................
0 to +18V
–V
CC
to ACOM .......................................................................... 0 to –18V
V
DD
to DCOM .............................................................................. 0 to +7V
V
DD
to ACOM ......................................................................................
±7V
ACOM to DCOM ..................................................................................
±7V
Digital Inputs (Pins 2–14, 16–19) to DCOM ...................... –0.4V to +18V
External Voltage Applied to 10V Range Resistor ............................
±12V
Ref Out ............................................................. Indefinite Short to ACOM
External Voltage Applied to DAC Output ................................ –5V to +5V
Power Dissipation ........................................................................ 1000mW
Lead Temperature (soldering, 10s) ............................................... +300°C
Max Junction Temperature ............................................................ +165°C
Thermal Resistance,
θ
J-A
: Plastic DIP and SOIC ....................... 100°C/W
NOTE: Stresses above those listed above may cause permanent damage to
the device. Exposure to absolute maximum conditions for extended periods
may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY
(LSB)
±1/2
LSB
±1/2
LSB
±1/2
LSB
DIFFERENTIAL
LINEARITY
(LSB)
3/4
3/4
3/4
PACKAGE
DRAWING
NUMBER
149
215
217
SPECIFICATION
TEMPERATURE
RANGE
–25°C to +85°C
0°C to +70°C
0°C to +70°C
PRODUCT
DAC811AH
DAC811JP
DAC811JU
PACKAGE
CerDIP-28
DIP-28
SOIC-28
ORDERING
NUMBER
(1)
DAC811AH
DAC811JP
DAC811JU
DAC811JU/1K
DAC811KP
DAC811KU
TRANSPORT
MEDIA
Rails
Rails
Rails
Tape and Reel
Rails
Rails
"
DAC811KP
DAC811KU
"
±1/4
LSB
±1/4
LSB
"
1/2
1/2
"
DIP-28
SOIC-28
"
215
217
"
0°C to +70°C
0°C to +70°C
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC811JU/1K” will get a single 1000-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC811
TIMING DIAGRAMS
Write Cycle #1
Load first rank from Data Bus: LDAC = 1
t
AW
Write Cycle #2
Load second rank from first rank: N
A
, N
B
, N
C
= 1
t
AW
LDAC
N
A
, N
B
, N
C
t
DW
DB
11
–DB
0
t
WP
WR
t
DH
t
WP
WR
t
SET
±1/2LSB
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
The DAC811 accepts positive-true binary input codes.
DAC811 may be connected by the user for any one of the
following codes: USB (unipolar straight binary), BOB (bi-
polar offset binary) or, using an external inverter on the
MSB line, BTC (binary two’s complement). See Table I.
DIGITAL INPUT
USB
Unipolar
Straight
Binary
+ Full Scale
+ 1/2 Full Scale
+ 1/2 Full Scale – 1LSB
Zero
ANALOG OUTPUT
BOB
Bipolar
Offset
Binary
+ Full Scale
Zero
–1LSB
– Full Scale
BTC
(1)
Binary
Two’s
Complement
–1LSB
– Full Scale
+ Full Scale
Zero
DRIFT
Gain drift is a measure of the change in the full scale range
(FSR) output over the specification temperature range. Drift is
expressed in parts per million per degree centigrade
(ppm/°C). Gain drift is established by testing the full scale
range value (e.g., +FS minus –FS) at high temperature, +25°C,
and low temperature, calculating the error with respect to the
+25°C value, and dividing by the temperature change.
Unipolar offset drift is a measure of the change in output
with all 0s on the input over the specification temperature
range. Offset is measured at high temperature, +25°C, and
low temperature. The offset drift is the maximum change in
offset referred to the +25°C value, divided by the tempera-
ture change. It is expressed in parts per million of full scale
range per degree centigrade (ppm of FSR/°C).
Bipolar zero drift is measured at a digital input of 800
16
, the
code that gives zero volts output for bipolar operation.
SETTLING TIME
Settling time is the total time (including slew time) for the
output to settle within an error band around its final value
after a change in input. Three settling times are specified to
±0.01%
of full scale range (FSR): two for maximum full
scale range changes of 20V and 10V, and one for a 1LSB
change. The 1LSB change is measured at the major carry
(7FF
16
to 800
16
and 800
16
to 7FF
16
), the input transition at
which worst-case settling time occurs.
REFERENCE SUPPLY
DAC811 contains an on-chip 6.3V reference. This voltage
(pin 28) has a tolerance of
±0.1V.
The reference output may
be used to drive external loads, sourcing at least 2mA. This
current should be constant for best performance of the D/A
converter.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
power supply change on the D/A converter output. It is
defined as a percent of FSR output change per percent of
change in either the positive, negative, or logic supply
voltages about the nominal voltages. Figure 1 shows typical
power supply rejection versus power supply ripple frequency.
MSB
LSB
↓
↓
111111111111
100000000000
011111111111
000000000000
NOTE: (1) Invert MSB of the BOB code with external inverter to obtain BTC code.
TABLE I. Digital Input Codes.
LINEARITY ERROR
Linearity error as used in D/A converter specifications by
Burr-Brown is the deviation of the analog output from a
straight line drawn between the end points (inputs all 1s and
all 0s). The DAC811 linearity error is specified at
±1/4LSB
(max) at +25°C for B and K grades, and
±1/2LSB
(max) for
A, J, and R grades.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from a
1LSB output change from one adjacent state to the next. A
DLE specification of 1/2LSB means that the output step size
can range from 1/2LSB to 3/2LSB when the input changes
from one state to the next. Monotonicity requires that DLE
be less than 1LSB over the temperature range of interest.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital inputs. All grades
of DAC811 are monotonic over their specification tempera-
ture range.
®
DAC811
4
1
Percent of FSR per Percent of
Change of Power Supply Voltage
–V
CC
0.1
The D/A latch is controlled by LDAC and WR. LDAC and
WR are internally NORed so that the latches transmit data to
the D/A switches when both LDAC and WR are at logic 0.
When either LDAC or WR are at logic 1, the data is latched
in the D/A latch and held until LDAC and WR go to logic 0.
All latches are level-triggered. Data present when the con-
trol signals are logic 0 will enter the latch. When any one of
the control signals returns to logic 1, the data is latched.
Table II is a truth table for all latches.
WR
N
A
X
0
1
1
1
0
N
B
X
1
0
1
1
0
N
C
X
1
1
0
1
0
LDAC
X
1
1
1
0
0
OPERATION
No operation
Enables input latch 4MSBs
Enables input latch 4 middle bits
Enables input latch 4LSBs
Loads D/A latch from input latches
Makes all latches transparent
0.01
V
DD
0.001
+V
CC
0.0001
10
100
1k
10k
100k
1M
Frequency (Hz)
FIGURE 1. Power Supply Rejection vs Power Supply Ripple
Frequency.
1
0
0
0
0
0
“X” = Don’t care.
OPERATION
DAC811 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference,
output amplifier, and microcomputer-compatible input logic
as shown in Figure 2.
INTERFACE LOGIC
Input latches A, B, and C hold data temporarily while a
complete 12-bit word is assembled before loading into the
D/A register. This double-buffered organization prevents the
generation of spurious analog output values. Each register is
independently addressable.
These input latches are controlled by N
A
, N
B
, N
C
, and WR.
N
A
, N
B
, and N
C
are internally NORed with WR so that the
input latches transmit data when both N
A
(or N
B
, N
C
) and
WR are at logic 0. When either N
A
, (N
B
, N
C
) or WR go to
logic 1, the input data is latched into the input registers and
held until both N
A
(or N
B
, N
C
) and WR go to logic 0.
TABLE II. DAC813 Interface Logic Truth Table.
GAIN AND OFFSET ADJUSTMENTS
Figures 3 and 4 illustrate the relationship of offset and gain
adjustments to unipolar and bipolar D/A converter output.
OFFSET ADJUSTMENT
For unipolar (USB) configurations, apply the digital input
code that should produce zero voltage output, and adjust the
offset potentiometer for zero output. For bipolar (BOB,
BTC) configurations, apply the digital input code that should
produce the maximum negative output voltage and adjust
the offset potentiometer for minus full scale voltage. Ex-
ample: If the full scale range is connected for 20V, the
maximum negative output voltage is –10V. See Table III for
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