(Features
•
Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
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– 1.8 (V
CC
= 1.8 to 5.5V)
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1 MHz (5.0V) and 400 KHz (1.8V Compatibility)
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Lead-free/Halogen-free Devices
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead
TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages.
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
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Description
The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32C/64C is
available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame
Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8-
ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 1.8V (1.8 to 5.5V) version.
AT24C32C
AT24C64C
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
8-lead Ultra Thin
Mini-MAP (MLP 2x3)
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
8-lead Ultra Lead Frame
Land Grid Array (ULA)
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
Not Recommended
for New Design
Bottom View
Bottom View
8-ball dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Bottom View
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
5298A–SEEPR–1/08
Absolute Maximum Ratings*
Operating Temperature ..................................... -55 to +125°C
Storage Temperature......................................... -65 to +150°C
Voltage on Any Pin
with Respect to Ground ....................................... -1.0 to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
1. Block Diagram
VCC
GND
WP
SCL
SDA
START
STOP
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A
2
A
1
A
0
R/W
COMP
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY
INC
LOAD
DATA WORD
ADDR/COUNTER
X DEC
EEPROM
Y DEC
SERIAL MUX
D
IN
D
OUT
D
OUT
/ACK
LOGIC
2
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
2. Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/ADDRESSES (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs that are
hard wired or left not connected for hardware compatibility with other AT24CXX devices. When
the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capaci-
tive coupling to the circuit board V
CC
plane is <3pF. If coupling is >3pF, Atmel
®
recommends
connecting the address pins to GND.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to V
CC
, all write operations to the memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive cou-
pling to the circuit board V
CC
plane is <3pF. If coupling is >3pF, Atmel recommends connecting
the pin to GND.
3
5298A–SEEPR–1/08
3. Memory Organization
AT24C32C/64C, 32/64K SERIAL EEPROM:
The 32K/64K is internally organized as 128/256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V to 5.5V
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40 to +85°C, V
CC
= +1.8 to +5.5V (unless otherwise noted)
Symbol
V
CC1
I
CC1
I
CC2
I
SB1
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Current
Supply Current
Standby Current
(1.8V option)
Input Leakage
Current V
CC
= 5.0V
Output Leakage
Current V
CC
= 5.0V
Input Low Level
(1)
Input High Level
(1)
Output Low Level
Output Low Level
V
CC
= 3.0V
V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 5.5V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
−0.6
V
CC
x 0.7
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
0.10
0.05
Test Condition
Min
1.8
0.4
2.0
Typ
Max
5.5
1.0
3.0
1.0
6.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
V
mA
mA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
4
AT24C32C/64C
5298A–SEEPR–1/08
AT24C32C/64C
AC Characteristics
Applicable over recommended operating range from T
AI
= -40°C to +85°C, V
CC
= +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted)
1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
i
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
0.6
50
5
1,000,000
0.05
1.3
0.6
0.6
0
100
0.3
300
0.25
50
5
1.3
0.6
100
0.9
0.05
0.5
0.25
0.25
0
100
0.3
100
Min
Max
400
0.4
0.4
50
0.55
Min
5.0-volt
Max
1000
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is ensured by characterization.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 kΩ (2.5V, 5.0V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
50 ns
Input and output timing reference voltages: 0.5 V
CC
5
5298A–SEEPR–1/08
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