EN27C512
EN27C512 512KBIT EPROM (64K x 8)
FEATURES
•
Fast Read Access Time
:
-
45, -55, -70, and -90ns
•
Single 5V Power Supply
•
Programming Voltage +12.75V
•
QuikRite
TM
•
Latch-Up Immunity to 100mA
from -1V to V
CC
+ 1V
•
Two-Line Control (
OE
&
CE
)
•
Standard Product Identification Code
•
JEDEC Standard Pinout
•
28-pin PDIP
•
32-pin PLCC
•
28-pin TSOP (Type 1)
•
Commercial and Industrial Temperature
Ranges
Programming Algorithm
•
Typical programming time 20µs
•
Low Power CMOS Operation
•
1µA Standby (Typical)
•
30mA Operation (Max.)
•
CMOS- and TTL-Compatible I/O
•
High-Reliability CMOS Technology
GENERAL DESCRIPTION
The EN27C512 is a low-power 512Kbit, 5V-only one-time-programmable (OTP) read-only
memory (EPROM). Organized into 64K words with 8 bits per word, it features QuikRite
TM
single-
address location programming, typically at 20µs per byte. Any byte can be accessed in less than
45ns, eliminating the need for WAIT states in high-performance microprocessor systems. The
EN27C512 has separate Output Enable (
OE
) and Chip Enable (
CE
) controls which eliminate
bus contention issues.
FIGURE 1. PDIP
Pin Name
A0-A15
DQ0-DQ7
Function
Addresses
Outputs
Chip Enable
Output Enable
No Connect
CE
OE
NC
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
1
Tel: 408-235-8680
Fax: 408-235-8685
EN27C512
FIGURE 2. TSOP
FIGURE 3. PLCC
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
2
Tel: 408-235-8680
Fax: 408-235-8685
EN27C512
FIGURE 4. BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
THE QUIKRITE
TM
PROGRAMMING OF THE EN27C512
When the EN27C512 is delivered, the chip has all 512K bits in the “ONE”, or
HIGH state. “ZEROs” are loaded into the EN27C512 through the procedure of programming.
The programming mode is entered when 12.75
±
0.25V is applied to the
OE
/V
PP
pin and
CE
is at V
IL
. For programming, the data to be programmed is applied with 8 bits in parallel to
the data pins.
The QUIKRITE programming flowchart in Figure 5 shows Eon’s interactive programming
algorithm. The interactive algorithm reduces programming time by using 20
µs
to 100
µs
programming pulses and giving each address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to a given address, the data in that
address is verified. If the data is not verified, additional pulses are given until it is verified or
until the maximum number of pulses is reached. This process is repeated while sequencing
through each address of the EN27C512. This part of the programming algorithm is done at
V
CC
= 6.25V to assure that each EPROM bit is programmed to a sufficiently high threshold
voltage. This ensures that all bits have sufficient margin. After the final address is completed,
the entire EPROM memory is read at V
CC
= 5.25
±
0.25V to verify the entire memory.
TM
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
3
Tel: 408-235-8680
Fax: 408-235-8685
EN27C512
PROGRAM INHIBIT MODE
Programming of multiple EN27C512 in parallel with different data is also easily accomplished
by using the Program Inhibit Mode. Except for
CE
, all like inputs of the parallel EN27C512
may be common. A TTL low-level program pulse applied to an EN27C512
CE
input with
OE
/V
PP
= 12.75
±
0.25V will program that EN27C512. A high-level
CE
input inhibits the
other EN27C512 from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits to determining that they were
correctly programmed. The verification should be performed with
OE
/V
PP
and
CE
at V
IL
. Data
should be verified at
t
DV
after the falling edge of
CE
.
AUTO PRODUCT IDENTIFICATION
The Auto Product Identification mode allows the reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode is intended for use by programming equipment
for the purpose of automatically matching the device to be programmed with its corresponding
programming algorithm. This mode is functional in the 25°C
±
5°C ambient temperature range
that is required when programming the EN27C512.
To activate this mode, the programming equipment must force 12.0 V
±
0.5V on address line A9
of the EN27C512. Two identifier bytes may then be sequenced from the device outputs by
toggling address line A0 from V
IL
to V
IH
, when A1 = V
IH
. All other address lines must be held at
V
IL
during Auto Product Identification mode.
Byte 0 (A0 = V
IL
) represents the manufacturer code, and byte 1 (A0 = V
IH
), the device code. For
the EN27C512, these two identifiers bytes are given in the Mode Select Table. All identifiers for
manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity
bit. When A1 = V
IL
, the EN27C512 will read out the binary code of 7F, continuation code, to
signify the unavailability of manufacturer ID codes.
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
4
Tel: 408-235-8680
Fax: 408-235-8685
EN27C512
READ MODE
The EN27C512 has two control functions, both of which must be logically satisfied in order to
obtain data at the outputs. Chip Enable (
CE
) is the power control and should be used for
device selection. Output Enable (
OE
) is the output control and should be used to gate data to
the output pins, independent of device selection. Assuming that addresses are stable,
address access time (t
ACC
) is equal to the delay from
CE
to output (t
CE
) . Data is available at
the outputs (t
OE
) after the falling edge of
OE
, assuming the
CE
has been LOW and
addresses have been stable for at least t
ACC
- t
OE
.
STANDBY MODE
The EN27C512 has CMOS standby mode which reduces the maximum V
CC
current to 20µA.
It is placed in CMOS standby when
CE
is at V
CC
±
0.3 V. The EN27C512 also has a TTL-
standby mode which reduces the maximum V
CC
current to 1.0 mA. It is placed in TTL-
standby when
CE
is at V
IH
. When in standby mode, the outputs are in a high-impedance
state, independent of the
OE
input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-line control function is provided to allow
for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that
CE
be decoded and used as the primary device-selection function, while
OE
be made a common connection to all devices in the array and connected to the READ line
from the system control bus. This assures that all deselected memory devices are in their low-
power standby mode and that the output pins are only active when data is desired from a
particular memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions, transient current peaks are produced
on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks
is dependent on the output capacitance loading of the device. At a minimum, a 0.1µF ceramic
capacitor (high frequency, low inherent inductance) should be used on each device between V
CC
and V
SS
to minimize transient effects. In addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on EPROM arrays, a 4.7µF bulk electrolytic
capacitor should be used between V
CC
and V
SS
for each eight devices. The location of the
capacitor should be close to where the power supply is connected to the array.
4800 Great America Parkway Ste 202
Santa Clara, CA. 95054
5
Tel: 408-235-8680
Fax: 408-235-8685
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