EN29F002 / EN29F002N
EN29F002 / EN29F002N
2 Megabit (256K x 8-bit) Flash Memory
FEATURES
•
5.0V ± 10% for both read/write operation
•
Read Access Time
- 45ns, 55ns, 70ns, and 90ns
•
Fast Read Access Time
- 70ns with C
load
= 100pF
- 45ns, 55ns with C
load
= 30pF
•
Sector Architecture:
One 16K byte Boot Sector, Two 8K byte
Parameter Sectors, one 32K byte and
three 64K byte main Sectors
•
Boot Block Top/Bottom Programming
Architecture
•
-
-
-
High performance program/erase speed
Byte program time: 10µs typical
Sector erase time: 500ms typical
Chip erase time: 3.5s typical
•
JEDEC standard
DATA
polling and toggle
bits feature
•
Hardware
RESET
Pin
(n/a for EN29F002N)
•
Single Sector and Chip Erase
•
Sector Protection / Temporary Sector
Unprotect (
RESET
= V
ID
)
•
Sector Unprotect Mode
•
Embedded Erase and Program Algorithms
•
Erase Suspend / Resume modes:
Read and program another sector during
Erase Suspend Mode
•
0.4 µm double-metal double-poly
triple-well CMOS Flash Technology
•
Low Vcc write inhibit < 3.2V
•
100K endurance cycle
•
Package Options
- 32-pin PDIP
- 32-pin PLCC
- 32-pin TSOP (Type 1)
•
Commercial and Industrial Temperature
Ranges
•
Low Standby Current
- 1µA CMOS standby current-typical
- 1mA TTL standby current
•
Low Power Active Current
- 30mA active read current
- 30mA program / erase current
•
JEDEC Standard program and erase
commands
GENERAL DESCRIPTION
The EN29F002 / EN29F002N is a 2-Megabit, electrically erasable, read/write non-volatile flash memory.
Organized into 256K words with 8 bits per word, the 2M of memory is arranged in seven sectors (with
top/bottom configuration), including one 16K Byte Boot Sector, two 8K Byte Parameter sectors, and four main
sectors (one 32K Byte and three 64K Byte). Any byte can be programmed typically at 10µs. The EN29F002 /
EN29F002N features 5.0V voltage read and write operation. The access times are as fast as 45ns to eliminate
the need for WAIT states in high-performance microprocessor systems.
The EN29F002 / EN29F002N has separate Output Enable (
OE
), Chip Enable (
CE
), and Write
Enable (
W E
) controls which eliminate bus contention issues. This device is designed to allow
either single sector or full chip erase operation, where each sector can be individually protected
against program/erase operations or temporarily unprotected to erase or program. The device can
sustain
a
minimum
of
100K
program/erase
cycles
on
each
sector.
4800 Great America Parkway, Suite 202
1
Santa Clara, CA 95054
Rev. C, Issue Date: 2001/07/05
Tel: 408-235-8680
Fax: 408-235-8685
Embedded System
京公网安备 11010802033920号
EEWORLD
