FH8065501516710S R1D1 datasheet, PDF

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FH8065501516710S R1D1: Descriptioncpu - central processing units atom c2518 quad core 1.7ghz fcbga1283; Categorysemiconductor Other integrated circuit (IC); File Size8MB，740 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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cpu - central processing units atom c2518 quad core 1.7ghz fcbga1283

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Intel

Atom™ Processor C2000

Product Family for Microserver

Datasheet

January 2014

Document Number: 330061-001

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

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Intel

Atom™ Processor C2000 Product Family for Microserver

Datasheet

January 2014

Document Number: 330061-001

C2000 Product Family for Microserver—Contents

Contents

Volume 1: C2000 Product Family for Microserver Program

Overview

...................................................................................... 31

Introduction and Product Offerings ..........................................................................32

1.1

Overview ..........................................................................................................32

1.2

Key Features.....................................................................................................33

1.3

Intel

Atom™ Processor C2000 Product Family for Microserver Block

Diagram ...........................................................................................................35

1.4

Product SKUs ....................................................................................................36

1.5

Datasheet Volume Structure and Scope ................................................................37

1.6

Terminology......................................................................................................39

1.7

Related Documents ............................................................................................44

Multi-Core Intel

Atom™ Processors ........................................................................46

2.1

Signal Descriptions ............................................................................................46

2.2

Features ...........................................................................................................46

2.3

SoC Components ...............................................................................................47

2.3.1

SoC Core .............................................................................................47

2.4

Features ...........................................................................................................48

2.4.1

Intel

Virtualization Technology ..............................................................48

2.4.2

Intel

VT-x Objectives ...........................................................................48

2.4.2.1

Intel

VT-x Features .............................................................49

2.4.3

Security and Cryptography Technologies ..................................................50

2.4.3.1

Advanced Encryption Standard New Instructions (AES-NI) .........50

2.4.3.2

PCLMULQDQ Instruction ........................................................50

2.4.3.3

Digital Random Number Generator..........................................50

2.4.4

Intel

Turbo Boost Technology ...............................................................50

2.4.4.1

Intel

Turbo Boost Technology Frequency................................51

2.5

CPUID Instruction and SoC Identification ..............................................................52

Volume 2: Functional

................................................................... 56

Memory Controller....................................................................................................57

3.1

Introduction ......................................................................................................57

3.2

Signal Descriptions ............................................................................................57

3.3

Features ...........................................................................................................58

3.3.1

Supported Memory Configuration ............................................................58

3.3.2

System Memory Technology Supported ....................................................58

3.4

RAS Features ....................................................................................................60

3.4.1

Data Parity Protection ............................................................................60

3.4.2

Memory Controller Error Correcting Codes (ECC) .......................................60

3.4.3

Demand and Patrol Scrubbing .................................................................62

3.4.4

DDR3 Data Scrambling ..........................................................................62

System Agent and Root Complex ..............................................................................63

4.1

Introduction ......................................................................................................63

4.2

Signal Descriptions ............................................................................................64

4.3

Features ...........................................................................................................64

4.4

Root Complex ...................................................................................................65

4.4.1

Transaction Flow ...................................................................................65

4.4.2

Root Complex Primary Transaction Routing ...............................................66

4.5

Reliability, Availability and Serviceability (RAS) ......................................................67

4.6

Error Classification .............................................................................................68

4.6.1

Correctable Errors .................................................................................69

Intel

Atom™ Processor C2000 Product Family for Microserver

Datasheet

January 2014

Document Number: 330061-001

Contents—C2000 Product Family for Microserver

4.7

4.8

4.9

4.10

4.11

4.12

Fatal Errors .......................................................................................... 69

Non-Fatal Errors ................................................................................... 69

4.6.3.1

Software Correctable Errors ................................................... 69

Global Error Reporting ....................................................................................... 70

4.7.1

Reporting Errors to CPU ......................................................................... 72

4.7.1.1

Non-Maskable Interrupt (NMI) ............................................... 72

4.7.1.2

System Management Interrupt (SMI) ...................................... 72

4.7.2

Reporting Global Errors to an External Device ........................................... 72

4.7.3

Machine Check Architecture.................................................................... 72

4.7.3.1

Machine Check Availability and Discovery ................................ 75

4.7.3.2

P5 Compatibility MSRs .......................................................... 75

4.7.3.3

Machine Check Global Control MSRs........................................ 76

4.7.3.4

Machine Check Error-Reporting MSR Banks 0-5 ........................ 77

4.7.4

Error-Status Cloaking Feature................................................................. 88

4.7.4.1

Hide Corrected-Error Status From OS...................................... 88

4.7.4.2

SMI for MCA Uncorrected Errors ............................................. 88

4.7.5

MCERR/IERR Signaling .......................................................................... 89

4.7.6

PCI Express INTx and MSI...................................................................... 89

4.7.7

Error Register Overview ......................................................................... 90

4.7.7.1

Local Error Registers............................................................. 91

4.7.7.2

Global Error Registers ........................................................... 93

4.7.7.3

System Error (SERR) ............................................................ 95

4.7.7.4

First and Next Error Log Registers .......................................... 95

4.7.7.5

Error Register Flow ............................................................... 96

4.7.7.6

Error Counters ..................................................................... 97

SoC Error Handling Summary ............................................................................. 98

System Agent Register Map .............................................................................. 106

4.10.1 Registers in Configuration Space ........................................................... 106

RAS Register Map............................................................................................ 107

4.11.1 Registers in Configuration Space ........................................................... 107

Root Complex Event Collector (RCEC) Register Map ............................................. 109

4.12.1 Registers in Configuration Space ........................................................... 109

4.6.2

4.6.3

Clock Architecture.................................................................................................. 111

5.1

Input Clocks ................................................................................................... 113

5.2

Output Clocks ................................................................................................. 114

Interrupt Architecture ........................................................................................... 115

6.1

PCI Interrupts and Routing ............................................................................... 115

6.2

Non-Maskable Interrupt (NMI) .......................................................................... 118

6.3

System Management Interrupt (SMI) ................................................................. 118

6.4

System Control Interrupt (SCI) ......................................................................... 119

6.5

Message Signaled Interrupt (MSI and MSI-X) ...................................................... 119

6.6

I/O APIC Input Mapping ................................................................................... 120

6.7

8259 PIC Input Mapping................................................................................... 122

6.8

Device Interrupt-Generating Capabilities ............................................................ 123

SoC Reset and Power Supply Sequences ................................................................ 125

7.1

Power Up from G3 State (Mechanical Off) ........................................................... 125

7.1.1

While in the G3 State .......................................................................... 125

7.1.2

Powering-Up for the First Time ............................................................. 125

7.1.3

SUS Power Well Power-Up Sequence From the G3 State........................... 126

7.1.4

Core Power-up Sequence ..................................................................... 129

7.2

Reset Sequences and Power-Down Sequences..................................................... 133

7.2.1

Cold Reset Sequence........................................................................... 133

7.2.1.1

SUSPWRDNACK ................................................................. 139

January 2014

Document Number: 330061-001

Intel

Atom™ Processor C2000 Product Family for Microserver

Datasheet

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Description	cpu - central processing units atom c2518 quad core 1.7ghz fcbga1283	cpu - central processing units atom c2308 dual core ext 1.7ghz fcbga1283	cpu - central processing units atom c2338 dual core 1.7ghz fcbga1283	cpu - central processing units atom c2538 quad core 2.4ghz fcbga1283	cpu - central processing units atom c2718 eight CR 2.0ghz fcbga1283	cpu - central processing units atom c2358 dual core 1.7ghz fcbga1283

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