12 / 8 CHANNEL LOW SIDE DRIVER WITH STALL DETECTION
PRODUCTION DATA - JUL 18, 2014
E520.01/02/03/08
Features
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
ÿ
8 or 12 high current outputs
R
ON
= 1.5Ω (typ.) I
MAX
= 350mA
Outputs combinable for higher loads
Digital voltage range VDD 3.3V or 5.0V
Low standby current < 1µA @50°C
Low output leakage < 5µA @13V, RT
SPI interface with diagnostics
Open load detection
Short circuit limitation, - detection
Output clamping for inductive loads typ. >40V
Thermal overload protection
-40°C to +125°C operation temperature (QFN)
General Description
The IC drives 2 or 3 unipolar stepper motors and pro-
vides an optional stall detection for end position detec-
tion. For LED dimming a quasi logarithmic duty cycle
is following the physiology of the human eye. With 3
PWM sources color LEDs can be driven in 3-color LED
mode (245Hz PWM). The Relay PWM mode automati-
cally adjusts the PWM to an effective supply voltage of
typ. 11V. All outputs are short circuit and over-temper-
ature protected with error read back capability. Switch
monitoring with control lamp combination with only 1
wire and output is possible.
Applications
ÿ
ÿ
ÿ
ÿ
ÿ
Stepper Motor Driver with Stall Detection
DC Motor Driver with PWM
Relay Driver with VBAT- automatically PWM
LED Driver with 3 logarithmic PWM sources
Switch Monitoring with pulsed current check and
control lamp
ÿ
Switch Monitoring with control lamp
Ordering Information
Product ID
E520.01
E520.02
E520.03
E520.08
Channels
12
12
8
8
X
Stall
Detection
X
Package
QFN32L5,
SOIC28
QFN32L5,
SOIC28
QFN32L5
QFN20L5,
SOIC20
QFN32L5
QFN20L5,
SOIC20
Typical Application Circuit
VBAT
D
VBAT
C
VBAT
VDD
VDD
C
VDD
VDD
VBAT_Sense
C
VBAT_Sense
Overtemp.
detection
Driver
control
Stall
detection*
4
Clamping
Current
Sense +
Limitation
OUT0-3
OUT4-7
OUT8-11
**
M
M
M
4
External
µC
ResetB
Sleep
mode
control
CEB
SCLK
SI
SO
Interface
E520.01, E520.02, E520.03, E520.08
* E520.01, E520.03 only
** E520.01, E520.02 only
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0054E.06
1/29
12 / 8 CHANNEL LOW SIDE DRIVER WITH STALL DETECTION
PRODUCTION DATA - JUL 18, 2014
E520.01/02/03/08
Functional Diagram
VDD
VBAT_SENSE
Overtemp.
detection
Driver
control
Stall
detection*
4
Clamping
Current
Sense +
Limitation
OUT0-3
OUT4-7
OUT8-11
**
4
RESETB
Sleep
mode
control
CEB
SCLK
SI
SO
Interface
E520.01, E520.02, E520.03, E520.08
* E520.01, E520.03 only
** E520.01, E520.02 only
Pin Configuration
Top View Not to Scale
OUT11
OUT10
Bottom Side
GND
nc
Top View Not to Scale
Pin 1
OUT6
OUT7
GND
nc
OUT11
OUT7
16
15
14
13
1
2
3
4
28
27
26
25
OUT10
GND
nc
nc
VDD
GND
RESETB
SO
SI
SCLK
CEB
GND
OUT9
OUT8
24 23 22 21 20 19 18 17
OUT5
OUT4
VBAT_SENSE
nc
TEST
nc
OUT0
OUT1
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
VDD
GND
GND
RESETB
SO
SI
SCLK
CEB
OUT6
GND
OUT5
OUT4
VBAT_SENSE
TEST
OUT0
OUT1
GND
OUT2
OUT3
nc
E520.xx
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
E520.xx
EP
12
11
10
9
nc
OUT2
OUT3
OUT8
OUT9
GND
nc
Pin 1
E520.01, E520.02 QFN32L5
GND
E520.01, E520.02 SOIC28
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0054E.06
2/29
12 / 8 CHANNEL LOW SIDE DRIVER WITH STALL DETECTION
PRODUCTION DATA - JUL 18, 2014
E520.01/02/03/08
Top View Not to Scale
OUT5
OUT6
OUT7
GND
Bottom Side
VDD
Top View Not to Scale
Pin 1
15 14 13 12 11
TEST
10
9
1
2
20
19
VBAT_SENSE
OUT4
OUT5
GND
OUT6
OUT7
nc
VDD
GND
RESETB
OUT4
VBAT_SENSE
nc
TEST
OUT0
16
17
18
19
20
1
GND
RESETB
SO
SI
SCLK
OUT0
OUT1
GND
OUT2
OUT3
CEB
SCLK
SI
SO
E520.xx
EP
2
3
4
5
8
7
6
E520.xx
3
4
5
6
7
8
9
10
18
17
16
15
14
13
12
11
OUT1
OUT2
OUT3
Pin 1
E520.03, E520.08 QFN20L5
GND
CEB
E520.03, E520.08 SOIC20
Top View Not to Scale
OUT6
OUT7
Bottom Side
GND
nc
nc
nc
GND
OUT5
OUT4
VBAT_SENSE
nc
TEST
nc
OUT0
OUT1
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
16
15
14
13
nc
VDD
GND
GND
RESETB
SO
SI
SCLK
CEB
E520.xx
EP
12
11
10
9
nc
nc
nc
OUT2
OUT3
GND
nc
Pin 1
E520.03, E520.08 QFN32L5
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
GND
Data Sheet
QM-No.: 25DS0054E.06
3/29
12 / 8 CHANNEL LOW SIDE DRIVER WITH STALL DETECTION
PRODUCTION DATA - JUL 18, 2014
E520.01/02/03/08
Pin Description
QFN32L5 QFN20L5 SOIC28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-
2)
14
15
16
17
18
19
-
20
1
-
2)
2
-
3
4
-
-
-
-
5
6
7
8
9
10
-
11
-
-
-
-
-
12
13
11
14
12
13
15
16
-
17
18
19
20
21
22
23
-
24
25
26
27
-
28
1
2
3
-
4
5
6
7
-
8
-
9
10
-
7
8
9
10
11
12
-
13
-
-
-
14
-
-
15
16
-
17
18
19
20
-
1
-
2
3
SOIC20
4
-
5
6
-
-
Name
GND
nc
OUT2
OUT3
OUT8
3)
OUT9
3)
nc
GND
CEB
SCLK
SI
SO
RESETB
GND
GND
VDD
-
-
GND
-
OUT10
3)
OUT11
3)
OUT7
OUT6
-
GND
OUT5
OUT4
VBAT_
SENSE
-
TEST
-
OUT0
OUT1
EP
O
O
S
I
S
O
O
I
O
O
O
O
S
O
O
S
S
I
I
I
O
I
O
O
O
O
Type
1)
S
Description
Common GND pin of driver 0 and driver 1
Common GND pin of driver 2 and driver 3
not connected
Low side open drain output driver 2
Low side open drain output driver 3
Low side open drain output driver 8
3)
Low side open drain output driver 9
3)
not connected
Common GND pin of driver 8 and driver 9
Chip Enable (Output data sampled on falling
edge of CEB, input data latched on rising edge)
Serial data input/output clock
(Data are clocked by the falling edge of SCLK)
Serial data input
Serial data output
(High impedance when CE = HIGH)
External reset (pull-down)
Ground
Ground
VDD supply voltage
leave open
leave open
Common GND pin of driver 10 and driver 11
not connected
Low side open drain output driver 10
3)
Low side open drain output driver 11
3)
Low side open drain output driver 7
Low side open drain output driver 6
not connected
Common GND pin of driver 4 and driver 5
Common GND pin of driver 6 and driver 7
Low side open drain output driver 5
Low side open drain output driver 4
VBAT Sense Pad (pull down)
not connected
Test mode enable (pull down)
For application use: Connect to ground
Low side open drain output driver 0
Low side open drain output driver 1
Exposed Die Pad
1) I/O = Input/Output, S= Supply
2) The exposed pad on the bottom side of the QFN is recommended to be connected to GND.
3) For the versions E520.03/08 this pins are not connected.
Note: Pins with identical names have to be connected.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0054E.06
4/29
12 / 8 CHANNEL LOW SIDE DRIVER WITH STALL DETECTION
PRODUCTION DATA - JUL 18, 2014
E520.01/02/03/08
1 Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress rat-
ings only; operation of the device at these or any other conditions beyond those listed in the operational sections of this document
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages
with respect to ground. Currents flowing into terminals are positive, those drawn out of a terminal are negative.
Description
Logic Supply Voltage
Transient Output Voltage
Output Current
Output Current (transient 500msec)
Input Voltage
Input Current
VBAT_SENSE Input Voltage
VBAT_SENSE Input Current
Junction Temperature
Ambient Temperature
1)
Storage Temperature
Thermal Resistance
Junction to Ambient QFN32L5
Thermal Resistance
Junction to Ambient QFN20L5
Thermal Resistance
Junction to Ambient SOIC28
3)
Thermal Resistance
Junction to Ambient SOIC20
3)
Power Dissipation
3)
Package QFN32L5
Power Dissipation
3)
Package QFN32L5
Power Dissipation
3)
Package QFN32L5
Connect pin TEST to GND
2)
Condition
Max. 500ms
Symbol
VDD
VOUT
IOUT
Min
-0.3
-0.3
Max
6
42
350
600
Unit
V
V
mA
mA
V
mA
V
mA
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
mW
mW
mW
Schaffner Pulse 2 IOUT
SPI interface pins VIN
SPI interface pins IIN
VBAT_SENSE
IVBAT_SENSE
TJ
TA
TSTG
R
TH,JA
R
TH,JA
R
TH,JA
R
TH,JA
T
A
< 85°C
T
A
< 105°C
T
A
< 125°C
PD
85
PD
105
PD
125
-0.3
-10
-0.3
-10
-40
-40
-40
21
22
71
76
VDD+0.3
10
42
10
150
125
150
23
24
87
94
2800
1950
1080
2)
1) The package was qualified at ambient temperatures -40...125°C,
for power dissipation < 1W also up to 150°C.
If higher ambient temperatures are focused please contact Elmos AG.
2) packages according to JEDEC standard JESD-51-6,7.
3) packages according to JEDEC standard JESD-51-5.
2) and 3) Using same structure on application board will lead to R
TH,JA
in the specified temperature region.
Power dissipation has to be taken into account based on R
TH,JA
values.
Actual thermal performance will depend on die-size, die-pad size, availability of an exposed die-pad and the concentration
of hot spots.
3) The maximum allowed power dissipation, calculated at TJ,max=150°C is a function of the ambient temperature and the
thermal resistance R
TH,JA
. It may be calculated as :
Pdmax=(TJ,max-TA)/RTH_JA.
Elmos Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0054E.06
5/29
京公网安备 11010802033920号
EEWORLD
