Intel
®
Ethernet Controller
I350
Datasheet
Networking Division (ND)
Features
External Interfaces provided:
PCIe v2.1 (2.5GT/s and 5GT/s) x4/x2/x1; called PCIe in this
document.
MDI (Copper) standard IEEE 802.3 Ethernet interface for
1000BASE-T, 100BASE-TX, and 10BASE-T applications
(802.3, 802.3u, and 802.3ab)
Serializer-Deserializer (SERDES) to support 1000BASE-SX/
LX (optical fiber - IEEE802.3)
Serializer-Deserializer (SERDES) to support 1000BASE-KX
(802.3ap) and 1000BASE-BX (PICMIG 3.1) for Gigabit
backplane applications
SGMII (Serial-GMII Specification) interface for SFP (SFP
MSA INF-8074i)/external PHY connections
NC-SI (DMTF NC-SI) or SMBus for Manageability connection
to BMC
IEEE 1149.6 JTAG
Power saving features:
Advanced Configuration and Power Interface (ACPI) power
management states and wake-up capability
Advanced Power Management (APM) wake-up functionality
Low power link-disconnect state
PCIe v2.1 LTR
DMA Coalescing for improved system power management
EEE (IEEE802.3az) for reduced power consumption during
low link utilization periods
IEEE802.1AS - Timing and Synchronization:
IEEE 1588 Precision Time Protocol support
Per-packet timestamp
Total Cost Of Ownership (TCO):
IPMI BMC pass-thru; multi-drop NC-SI
Internal BMC to OS and OS to BMC traffic support
Performance Enhancements:
PCIe v2.1 TLP Process Hints (TPH)
UDP, TCP and IP Checksum offload
UDP and TCP Transmit Segmentation Offload (TSO)
SCTP receive and transmit checksum offload
Additional product details:
17x17 (256 Balls) or 25x25 (576 Balls) PBGA package
Estimated power: 2.8W (max) in dual port mode and 4.2W
(max) in quad port mode
Memories have Parity or ECC protection
Virtualization ready:
Next Generation VMDq support (8 VMs)
Support of up to 8 VMs per port (1 queue allocated to each
VM)
PCI-SIG I/O SR-IOV support (Direct assignment)
Queues per port: 8 TX and 8 RX queues
Revision 2.2
January 2014
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Copyright © 2008-2014. Intel Corporation. All Rights Reserved.
L
2
Revision History — Intel
®
Ethernet Controller I350
Revision History
Rev
.3
.5
1.0
1.1
1.9
Date
1/8/2010
5/21/2010
1/7/2011
4/6/2011
4/14/2011
Initial public release.
Updated using latest internal specs.
Updated using latest internal specs.
Updated using latest internal specs.
Updated with latest internal specs.
Version number moved to 1.9 for PRQ.
Added or updated:
•
Section 6.4.2, Port Identification LED blinking (Word 0x04)
•
Section 13.1, Thermal Sensor and Thermal Diode
• Updated power numbers.
Added (improves coverage of 2-port 17X17 package):
•
Section 2.2.13, 2-Port 17x17 PBGA Package Pin List (Alphabetical)
•
Section 2.2.14, 2-Port 17x17 PBGA Package No-Connect Pins
Updated.
•
Section 1.6, I350 Packaging Options.
Updated to cover both 17x17 options.
•
Section 11-5, Flash Timing Diagram.
Removed meaningless line from diagram.
•
Section 11.7.1.1, 17x17 PBGA Package Schematics.
Corrected display issue
with diagram.
SRA release.
• RSVD_TX_TCLK was expressed as 1.25MHZ (clock speed). Corrected to
125MHz in two places. See
Table 2-10, Analog Pins, Table 2-23, PHY Analog
Pins.
•
Section 11.7.2.1, 25x25 PBGA Package Schematics.
Diagram updated.
•
Section 8.5.5, Flow Control Receive Threshold Low - FCRTL0 (0x2160; R/W).
Changed: “at least 1b (at least 16 bytes)” to “3b (at least 48 bytes) Diagram
updated”.
Figure 7-26, Figure 7-26
build issues corrected.
Section 10.6.3.16, Thermal Sensor Commands.
Note added (“Thermal Sensor
configuration can be done only through NC-SI channel 0.”).
Section 6.2.22, Functions Control (Word 0x21),
bit 9 note;
Section 9.4.11.4,
Base Address Register Fields,
bit 9 description. Both contain the updated text:
“This bit should be set only on systems that do not generate prefetchable
cycles.”
Section 8.26.1, Internal PHY Configuration - IPCNFG (0x0E38, RW)
and
Section 8.26.2, PHY Power Management - PHPM (0x0E14, RW);
tables
reformatted.
Table 10-49, Driver Info Host Command,
Byte 1; description updated.
Table 11-6, Power Consumption 2 Ports,
D0a - Active Link row, total power
column has been corrected.
Section 5.1.1, PCI Device Power States.
Section updated. See text starting
with “The PCIe link state follows the power management state of the device...”
Section 6.3.11, NC-SI Configuration Module (Global MNG Offset 0x0A).
Register descriptions for a number off offsets have been updated. These
include: Offsets 0x01, 0x03, 0x05, and 0x07
Table 8-10, Usable FLASH Size and CSR Mapping Window Size.
Table added to
Datasheet.
Table 10-30, Supported NC-SI Commands.
“Set Ethernet Mac Address”
corrected to “Set MAC Address”. “Clear Ethernet MAC Address” removed from
supported. This is an obsolete reference.
Comments
1.91
5/6/2011
1.92
5/10/2011
1.93
5/20/2011
2.00
6/23/2011
2.01
6/24/2011
2.02
8/2/2011
•
•
•
•
2.03
8/25/2011
•
•
•
•
2.04
9/16/2011
•
•
3
Intel
®
Ethernet Controller I350 — Revision History
Rev
Date
•
•
Comments
Section 6.3.12.2, Traffic Type Data - Offset 0x1.
Default values of 01 added for
all traffic types.
Section 6.4.9, Reserved/3rd Party External Thermal Sensor – (Word 0x3E).
New reserved section added.
Section 8.16.28.1, Time Sync Interrupt Cause
Register - TSICR (0xB66C; RC/W1C).
Note in section updated. New text:
“Once ICR.Time_Sync is set, TSICR should be read to determine the actual
interrupt cause and to enable reception of an additional ICR.Time_Sync
interrupt.”
Figure 12-6:
Updated to correct error.
Section 12.5, Oscillator Support:
Contains similar update in the section’s first bullet.
Section 3.1.7.9, Completion with Completer Abort (CA).
The discussion has
been corrected. The updated paragraph is: “A DMA master transaction ending
with a Completer Abort (CA) completion causes all PCIe master transactions to
stop; the PICAUSE.ABR bit is set and an interrupt is generated if the
appropriate mask bits are set. To enable PCIe master transactions following
reception of a CA completion, software issues an FLR to the right function or a
PCI reset to the device and re-initializes the function(s).”
Section 6.3.9.17, NC-SI over MCTP Configuration - 0ffset 0x10.
Phrase in bit 7
description updated. New text: “If cleared, a payload type byte is expected in
NC-SI over MCTP packets after the packet type...”
Section 6.4.3, EEPROM Image Revision (Word 0x05).
Table updated; bit
assignment descriptions changed. Changed to: 15:12 EEPROM major version;
11:8 are reserved; 7:0 EEPROM minor version. Example given in note.
Section 9.6.6.2, LTR Capabilities (0x1C4; RW).
The reserved fields (bits 15:13
and 31:29) now indicate RO, not RW.
Figure 11-11 : Coupling cap data in figure corrected;
changed 10pf to 1000pf.
Table 12-4, Crystal Manufacturers and Part Numbers.
Footnote added to table
for 7A25000165. Text states: “This part footprint compatible with X540
designs.”
2.05
12/20/2011
•
•
•
2.06
4/10/2012
•
•
•
•
4
Revision History — Intel
®
Ethernet Controller I350
Rev
Date
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Comments
Section 2.3.4, NC-SI Interface Pins.
Notes added. They specify pull-ups/downs
used when NC-SI is disconnected.
Section 7.8.2.2.5, Serial ID.
New text provided: “The serial ID capability is not
supported in VFs.”
Section 8.8.10, Interrupt Cause Set Register - ICS (0x1504; WO).
Time Sync
(bit 19) exposed.
Table 11-6, Power Consumption 2 Ports.
Some numbers updated. See bold
copy.
Revised
Table 2-15
- 2-Port 17x17 PBGA Package Pin List (Alphabetical); SDP2
and SDP3 connections.
Revised
Section 2.3.8
(Power Supply and Ground Pins); removed C4.
Revised
Section 2.3.9
(25x25 PBGA Package Pin List (Alphabetical); C4 signal
name change.
Revised
Section 3.7.6.3.1
(Setting Powerville to Internal PHY loopback Mode);
added new bullet.
Revised
Section 4.3.5
(Registers and Logic Reset Affects); step 10.
Revised
Section 6.2.17
(PCIe Control 1 (Word 0x1B); bit 14 description.
Revised
Section 6.3.9.17
(NC-SI over MCTP Configuration - 0ffset 0x10); bit 7
description.
Added
Section 6.4.6.11
through
Section 6.4.6.18
and (PXE VLAN Configuration
Pointer (0x003C) bit descriptions.
Revised
Table 8-6
- Register Summary); Management Flex UDP/TCP Ports
address.
Revised
Section 8.8.9
(Interrupt Cause Read Register - ICR (0x1500; RC/
W1C); bit 20 description.
Revised
Section 10.5.8.1
(Transmit Errors in Sequence Handling); note after
table 10-10.
Revised
Section 10.7.1.3
(Simplified MCTP Mode); removed payload type
references.
Revised
Section 10.7.4.1
(NC-SI Packets Format).
Added
Section 10.7.4.1.1
(Control Packets).
Revised
Section 10.7.4.1.2
(Command Packets); payload type and message
type.
Revised
Section 10.7.4.1.3
(Response Packets); payload type and message
type.
Revised
Section 11.3.1
(Power Supply Specification); added second footnote.
Added
Section 3.7.6.6, Line Loopback.
Section 6.2.24, Initialization Control 3 (LAN Base Address + Offset 0x24)
—
Updated description of Com_MDIO field.
Section 8.1.3, Register Summary
— Corrected offset value for VFMPRC in Table
8-6.
Section 8.27.3, Register Set - CSR BAR
— Corrected Virtual Address and
Physical Address Base values for VFMPRC in associated table.
Section 8.28.43, Multicast Packets Received Count - VFMPRC (0x0F38; RO)
—
Corrected address value.
Section 10.6.2, Supported Features,
Table 10-30 — Changed “Supported over
MCTP” value from No to Yes for “Select Package” and “Deselect Package”
commands.
Figure 11-5 — Changed Output Valid symbol from T
Val
to T
V
to match
description in Table 11-15.
Figure 11-6 — Changed Output Valid symbol from T
Val
to T
V
to match
description in Table 11-16.
Section 13.5.4, Package Thermal Characteristics
— Revised text related to
Flotherm* models.
2.1
3/22/2013
2.2
1/27/14
•
•
•
•
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