Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics—Single Supply
(V
CC
= 5V, V
EE
= 0V, V
CM
= V
CC
/2, V
OUT
= V
CC
/2, R
L
= ∞ to V
CC
/2,
DISABLE_
= V
CC
(MAX4389/MAX4393/MAX4394/MAX4396),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Input Common-Mode Voltage
Range
Input Offset Voltage
Input Offset Voltage Matching
Input Offset Voltage Tempco
Input Bias Current
Input Offset Current
Input Resistance
Common-Mode Rejection Ratio
Open-Loop Gain
TC
VOS
I
B
I
OS
R
IN
CMRR
A
VOL
Differential mode (-1V ≤ V
IN
≤ +1V)
Common mode (-0.2V ≤ V
CM
≤ +2.75V)
(V
EE
- 0.2V) ≤ V
CM
≤ (V
CC
- 2.25V)
0.25V ≤ V
OUT
≤ 4.75V, R
L
= 2kΩ
0.8V ≤ V
OUT
≤ 4.5V, R
L
= 150Ω
1V ≤ V
OUT
≤ 4V, R
L
= 50Ω
R
L
= 2kΩ
R
L
= 150Ω
Output Voltage Swing
V
OUT
R
L
= 75Ω
R
L
= 75Ω to
ground
Output Current
Output Short-Circuit Current
I
OUT
I
SC
V
CC
- V
OH
V
OL
- V
EE
V
CC
- V
OH
V
OL
- V
EE
V
CC
- V
OH
V
OL
- V
EE
V
CC
- V
OH
V
OL
- V
EE
40
40
70
50
50
SYMBOL
V
CM
V
OS
CONDITIONS
Guaranteed by CMRR test
T
A
= +25°C
T
A
= -40°C to +85°C
MAX4392–MAX4396
1
15
2.5
0.2
70
3
95
70
60
58
0.065
0.05
0.3
0.25
0.5
0.45
1
0.025
55
50
±100
0.25
0.15
0.5
0.5
0.8
0.8
1.7
0.1
mA
mA
V
dB
15
5
MIN
V
EE
-
0.2
5
TYP
MAX
V
CC
-
2.25
18
26
UNITS
V
mV
mV
µV/°C
µA
µA
kΩ
MΩ
dB
Sinking from R
L
= 75Ω to V
CC
Sourcing into R
L
= 75Ω to V
EE
Sinking or sourcing
www.maximintegrated.com
Maxim Integrated │ 2
MAX4389/MAX4390/
MAX4392–MAX4396
Ultra-Small, Low-Cost, 85MHz Op Amps with
Rail-to-Rail Outputs and Disable
DC Electrical Characteristics—Single Supply (continued)
(V
CC
= 5V, V
EE
= 0V, V
CM
= V
CC
/2, V
OUT
= V
CC
/2, R
L
= ∞ to V
CC
/2,
DISABLE_
= V
CC
(MAX4389/MAX4393/MAX4394/MAX4396),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Open-Loop Output Resistance
Power-Supply Rejection Ratio
Operating Supply Voltage Range
Disabled Output Resistance
DISABLE_
Logic-Low Threshold
DISABLE_
Logic-High Threshold
DISABLE_
Logic-Input Low
Current
DISABLE_
Logic-Input High
Current
Quiescent Supply Current
(Per Amplifier)
SYMBOL
R
OUT
PSRR
V
S
R
OUT(OFF
)
V
IL
V
IH
I
IL
I
IH
I
S
V
DISABLE_
= 0V
DISABLE_
= V
CC
DISABLE_
= V
CC
V
DISABLE_
= 0V
V
CC
- 1.25
20
5
3.2
0.3
60
40
5
0.4
V
EE
= 0V, V
CC
= 4.5V to 5.5V
Guaranteed by PSRR
V
DISABLE_
= 0V, 0 ≤ V
OUT
≤ 5V
48
4.5
40
95
V
CC
- 3
CONDITIONS
MIN
TYP
8
65
11
MAX
UNITS
Ω
dB
V
kΩ
V
V
µA
µA
mA
DC Electrical Characteristics—Dual Supply
(V
CC
= 5V, V
EE
= -5V, V
CM
= 0V, V
OUT
= 0V, R
L
= ∞ to 0,
DISABLE_
= V
CC
(MAX4389/MAX4393/MAX4394/MAX4396),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Input Common-Mode Voltage
Input Offset Voltage
Input Offset Voltage Matching
Input Offset Voltage Tempco
Input Bias Current
Input Offset Current
Input Resistance
Common-Mode Rejection Ratio
Open-Loop Gain
TC
VOS
I
B
I
OS
R
IN
CMRR
A
VOL
Differential mode (-1V ≤ V
IN
≤ +1V)
Common mode (-0.2V ≤ V
CM
≤ +2.75V)
V
EE
≤ V
CM
≤ (V
CC
- 2.25V)
-4.5V ≤ V
OUT
≤ 4.5V, R
L
= 2kΩ
-4.25V ≤ V
OUT
≤ 4.25V, R
L
= 150Ω
70
65
50
SYMBOL
V
CM
V
OS
T
A
= +25°C
T
A
= -40°C to +85°C
MAX4392–MAX4396
1
20
5
0.5
70
3
90
80
60
15
5
CONDITIONS
Guaranteed by CMRR test
MIN
V
EE
7
TYP
MAX
V
CC
- 2.25
20
28
UNITS
V
mV
mV
µV/°C
µA
µA
kΩ
MΩ
dB
dB
www.maximintegrated.com
Maxim Integrated │ 3
MAX4389/MAX4390/
MAX4392–MAX4396
Ultra-Small, Low-Cost, 85MHz Op Amps with
Rail-to-Rail Outputs and Disable
DC Electrical Characteristics—Dual Supply (continued)
(V
CC
= 5V, V
EE
= -5V, V
CM
= 0V, V
OUT
= 0V, R
L
= ∞ to 0,
DISABLE_
= V
CC
(MAX4389/MAX4393/MAX4394/MAX4396),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
R
L
= 2kΩ
Output Voltage Swing
V
OUT
R
L
= 150Ω
R
L
= 75Ω
Output Current
Output Short-Circuit Current
Open-Loop Output Resistance
Power-Supply Rejection Ratio
Operating Supply Voltage Range
Disabled Output Resistance
DISABLE_
Logic-Low Threshold
DISABLE_
Logic-High Threshold
Quiescent Supply Current
(Per Amplifier)
I
OUT
I
SC
R
OUT
PSRR
V
S
R
OUT(OFF)
V
IL
V
IH
I
S
DISABLE_
= V
CC
V
DISABLE_
= 0V
V
CC
- 1.25
6
0.45
10
0.8
V
EE
= 0V, V
CC
= 4.5V to 5.5V
Guaranteed by PSRR
V
DISABLE_
= 0V, -5V ≤ V
OUT
≤ +5V
48
4.5
40
95
V
CC
- 3
CONDITIONS
V
CC
- V
OH
V
OL
- V
EE
V
CC
- V
OH
V
OL
- V
EE
V
CC
- V
OH
V
OL
- V
EE
50
50
MIN
TYP
0.175
0.075
0.575
0.4
1.5
0.75
95
75
±100
8
60
11
MAX
0.3
0.2
0.85
1.5
2.35
1.6
mA
mA
Ω
dB
V
kΩ
V
V
mA
V
UNITS
Sinking from R
L
= 75Ω to V
CC
Sourcing into R
L
= 75Ω to V
EE
Sinking or sourcing
AC Electrical Characteristics—Single Supply
(V
CC
= 5V, V
EE
= 0V, V
CM
= 1.5V, R
L
= 100Ω to V
CC
/2,
DISABLE_
= V
CC
(MAX4389/MAX4393/MAX4394/MAX4396),
V
OUT
= V
CC
/2, A
VCL
= 1V/V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Small-Signal -3dB Bandwidth
Large-Signal -3dB Bandwidth
Small-Signal 0.1dB Gain
Flatness
Large-Signal 0.1dB Gain
Flatness
Slew Rate
Settling Time to 0.1%
Rise/Fall Time
Spurious-Free Dynamic Range
SYMBOL
BW
SS
BW
LS
BW
0.1dBSS
BW
0.1dBLS
SR
t
s
t
R
/t
F
SFDR
CONDITIONS
V
OUT
= 100mV
P-P
V
OUT
= 2V
P-P
V
OUT
= 100mV
P-P
V
OUT
= 2V
P-P
V
OUT
= 2V step
V
OUT
= 2V step
V
OUT
= 100mV
P-P
f
C
= 5MHz, V
OUT
= 2V
P-P
MIN
TYP
72
80
30
30
500
28
4
-59
MAX
UNITS
MHz
MHz
MHz
MHz
V/µs
ns
ns
dBc
www.maximintegrated.com
Maxim Integrated │ 4
MAX4389/MAX4390/
MAX4392–MAX4396
Ultra-Small, Low-Cost, 85MHz Op Amps with
Rail-to-Rail Outputs and Disable
AC Electrical Characteristics—Single Supply (continued)
(V
CC
= 5V, V
EE
= 0V, V
CM
= 1.5V, R
L
= 100Ω to V
CC
/2,
DISABLE_
= V
CC
(MAX4389/MAX4393/MAX4394/MAX4396),
V
OUT
= V
CC
/2, A
VCL
= 1V/V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
Differential Phase Error
Differential Gain Error
Input Noise-Voltage Density
Input Noise-Current Density
Input Capacitance
Output Impedance
Disable OFF Time
Disable ON Time
Channel-to-Channel Isolation
CH
ISO
SYMBOL
DP
DG
e
n
i
n
C
IN
Z
OUT
f = 5MHz
MAX4389/MAX4393/MAX4394/MAX4396
MAX4389/MAX4393/MAX4394/MAX4396
MAX4392–MAX4396, specified at DC
CONDITIONS
NTSC, R
L
= 150Ω
NTSC, R
L
= 150Ω
f = 10kHz
f = 10kHz
MIN
TYP
0.015
0.015
13
2.1
1
0.6
80
40
-97
MAX
UNITS
degrees
%
nV/√Hz
pA/√Hz
pF
Ω
ns
ns
dB
AC Electrical Characteristics —Dual Supply
(V
CC
= 5V, V
EE
= -5V, R
L
= ∞ to GND, GND = 0, V
OUT
= 0V, Gain = 1V/V,
DISABLE
= V
CC
, and T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
PARAMETER
Small-Signal -3dB Bandwidth
Large-Signal -3dB Bandwidth
Small-Signal Bandwidth for
0.1dB Gain Flatness
Large-Signal Bandwidth for
0.1dB Gain Flatness
Slew Rate
Settling Time to 0.1%
Rise/Fall Time
Spurious-Free Dynamic Range
Differential Phase Error
Differential Gain Error
Input Noise-Voltage Density
Input Noise-Current Density
Input Capacitance
Output Impedance
Disable OFF Time
Disable ON Time
Channel-to-Channel Isolation
CH
ISO
SYMBOL
BW
SS
BW
LS
BW
0.1dBss
BW
0.1dBLS
SR
t
S
t
R
/t
F
SFDR
DP
DG
e
n
i
n
C
IN
Z
OUT
f = 5MHz
MAX4389/MAX4393/MAX4394/MAX4396
MAX4389/MAX4393/MAX4394/MAX4396
MAX4392/MAX4393/MAX4394/MAX4395/
MAX4396, specified at DC
CONDITIONS
V
OUT
= 100mV
P-P
V
OUT
= 2V
P-P
V
OUT
= 100mV
P-P
V
OUT
= 2V
P-P
V
OUT
= 2V step
V
OUT
= 2V step
V
OUT
= 100mV
P-P
f
C
= 5MHz, V
OUT
= 2V
P-P
NTSC, R
L
= 150Ω
NTSC, R
L
= 150Ω
f = 10kHz
f = 10kHz
MIN
TYP
85
90
27
24
500
21
4
-59
0.015
0.015
13
2.1
1
0.6
80
40
-97
MAX
UNITS
MHz
MHz
MHz
MHz
V/µs
ns
ns
dBc
degrees
%
nV/√Hz
pA/√Hz
pF
Ω
ns
ns
dB
Note 2:
All devices are 100% production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by design.
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