CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VCC SUPPLY CURRENT
Nominal Supply Current
Recommended Operating Conditions.
Boldface limits apply over the operating temperature range, 0°C to
+70°C.
SYMBOL
I
5VSB
TEST CONDITIONS
V
S3
= 5V, V
S5
= 5V (S0 State)
V
S3
= 0V, V
S5
= 5V (S3 State)
V
S5
= 0V (S5 State)
MIN
MAX
(Note 6) TYP (Note 6) UNITS
-
-
-
-
3.60
1.00k resistor between DLA and 12V Rail
V
5VSBY
= 5.0V, I
3V3SB
= 0A
V
3V3SB
V
3V3SB_UV
I
3V3SB_TRIP
ISL6506, ISL6506A
ISL6506B
8.9
-
-
-
-
-
20
-
t
SS
6.55
-
-
0.8
-
-
3.60
4.60
4.60
-
-
9.8
-
3.3
2.475
-
-
-
58
8.2
-7.5
-
-
10
140
-
-
-
4.5
3.95
10.8
2.0
-
-
1
2
35
-
9.85
-
2.2
-
-
-
mA
mA
mA
V
V
V
%
V
V
A
A
mA
µs
ms
µA
V
V
µA
°C
POWER-ON RESET
Rising 5VSB POR Threshold
Falling 5VSB POR Threshold
Rising 12V POR Threshold
3.3V
AUX
LINEAR REGULATOR
Regulation
3V3SB Nominal Voltage Level
3V3SB Undervoltage Threshold
3V3SB Overcurrent Trip
5V
DUAL
SWITCH CONTROLLER
5VDLSB Output Drive Current
TIMING INTERVAL
S0 to S3 Transition Delay
SOFT-START
Soft-start Interval
5VDLSB Soft-start Current Source
CONTROL I/O (S3, S5)
High Level Input Threshold
Low Level Input Threshold
S3, S5 Internal Pull-down Current to GND
TEMPERATURE MONITOR
Shutdown-Level Threshold
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
I
5VDLSB
V
5VDLSB
= 4V
,
V
5VSB
= 5V
FN9141 Rev 7.00
Nov 10, 2015
Page 3 of 9
ISL6506, ISL6506A, ISL6506B
Functional Pin Description
VCC (Pin 1)
Provide a very well decoupled 5V bias supply for the IC to
this pin by connecting it to the ATX 5V
SB
output. This pin
provides all the bias for the IC as well as the input voltage for
the internal standby 3V3AUX LDO. The voltage at this pin is
monitored for power-on reset (POR) purposes.
controller/regulator supplying the computer system’s
3.3V
DUAL
power, a dual switch controller supplying the
5V
DUAL
voltage, as well as all the control and monitoring
functions necessary for complete ACPI implementation.
Initialization
The ISL6506 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V
SB
input supply voltage. The ISL6506 also
monitors the 12V rail to insure that the ATX rails are up
before entering into the S0 state even if both SLP_S3 and
SLP_S5 are both high.
GND (Pin 5, Pad)
Signal ground for the IC. These pins are also the ground
return for the internal 3V3AUX LDO that is active in
S3/S4/S5 sleep states. All voltage levels are measured with
respect to these pins.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3V
DUAL
and 5V
DUAL
outputs. The internal circuitry does
not allow the transition from an S4/S5 state to an S3 state.
TABLE 1. 5V
DUAL
OUTPUT TRUTH TABLE
S5
1
1
0
0
0
S3
1
0
1
0
0
3.3V
3.3V
3.3AUX
3.3V
3.3V
Note
0V
5V
5VDL
5V
5V
COMMENTS
S0/S1/S2 States (Active)
S3
Maintains Previous State
S4/S5 (ISL6506 and
ISL6506B)
S4/S5 (ISL6506A)
S3 and S5 (Pins 3 and 4)
These pins switch the IC’s operating state from active (S0,
S1/S2) to S3 and S4/S5 sleep states. These are digital
inputs featuring internal 10µA pull-down current sources on
each pin. Additional circuitry blocks illegal state transitions,
such as S4/S5 to S3. Connect S3 and S5 to the computer
system’s SLP_S3 and SLP_S5 signals, respectively.
3V3AUX (Pin 2)
Connect this pin to the 3V3DUAL output. In sleep states, the
voltage at this pin is regulated to 3.3V through an internal
pass device powered from 5VSBY through the VCC pin. In
active states, ATX 3.3V output is delivered to this node
through a fully-on NMOS transistor. During S3 and S4/S5
states, this pin is monitored for undervoltage events.
NOTE: Combination Not Allowed.
DLA (Pin 6)
This pin is an open-drain output. A 1k resistor must be
connected from this pin to the ATX 12V output. This resistor
is used to pull the gates of suitable N-MOSFETs to 12V,
which in active state, switch in the ATX 3.3V and 5V outputs
into the 3.3V
AUX
and 5V
DUAL
outputs, respectively. This pin
is also used to monitor the 12V rail during POR. If a resistor
other than 1k is used, the POR level will be affected.
Functional Timing Diagrams
Figures 1 (ISL6506, ISL6506B) and 2 (ISL6506A) are simplified
timing diagrams, detailing the power-up/down sequences of all
the outputs in response to the status of the sleep-state pins (S3,
S5), as well as the status of the input ATX supply. Not shown in
these diagrams is the deglitching feature used to protect
against false sleep state tripping. Additionally, the ISL6506
features a 60µs delay in transitioning from S0 to S3 states. The
transition from the S0 state to S4/S5 state is immediate.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
ISL6506 and ISL6506B: In S3 sleep state, this transistor is
switched on, connecting the ATX 5V
SB
output to the 5V
DUAL
regulator output.
ISL6506A: In S3 and S4/S5 sleep state, this transistor is
switched on, connecting the ATX 5V
SB
output to the 5V
DUAL
regulator output.
5VSB
S3
S5
3.3V, 5V, 12V
DLA
3V3AUX
5VDLSB
5VDL
Description
Operation
The ISL6506 controls 2 output voltages, 3.3V
DUAL
and
5V
DUAL
. It is designed for microprocessor computer
applications requiring 3.3V, 5V, 5V
SB
, and 12V bias input
from an ATX power supply. The IC is composed of one linear
FIGURE 1. 5V
DUAL
AND 3.3V
AUX
TIMING DIAGRAM;
ISL6506 AND ISL6506B
FN9141 Rev 7.00
Nov 10, 2015
Page 4 of 9
ISL6506, ISL6506A, ISL6506B
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
5VSB
S3
S5
5VSB
(1V/DIV)
3.3V, 5V, 12V
DLA
3V3DL
0V
5VDLSB
5VDL
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
DLA
(10V/DIV)
FIGURE 2. 5V
DUAL
AND 3.3V
AUX
TIMING DIAGRAM;
ISL6506A
t0
t1
t2
t3
t4 t5
TIME
t6
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5V
SB
(bias)
is applied to the circuit. At time t1, the 5V
SB
surpasses POR
level. Time t2, one soft-start interval after t1, denotes the
initiation of soft-start. The 3.3V
DUAL
rail is brought up
through the internal standby LDO through an internal digital
soft-start function. Figure 4 shows the 5V
DUAL
rail initiating a
soft-start at time t2 as well. The ISL6506A will draw 7.5µA
into the 5VDLSB for a duration of one soft-start period. This
current will enhance the P-MOSFET (Q
2
, refer to
?$paratext>? on page 2) in a controlled manner. At time t3,
the 3.3V
DUAL
is in regulation and the 5VDLSB pin is pulled
down to ground. If the 5V
DUAL
rail has not reached the level
of the 5V
SB
rail by time t3, then the rail will experience a
sudden step as the P-MOSFET gate is fully enhanced. The
soft-start profile of the 5V
DUAL
may be altered by placing a
capacitor between the gate and drain of the P-MOSFET.
Adding this capacitor will increase the gate capacitance and
slow down the start of the 5V
DUAL
rail.
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506,
ISL6506B (Figure 3), the 5V
DUAL
rail will begin to ramp-up
from the 5V
ATX
rail through the body diode of the N-MOSFET
(Q
3
). The ISL6506A will already have the 5V
DUAL
rail in
regulation (Figure 4). At time t5, the 12V
ATX
rail has
surpassed the 12V POR level. Time t6 is three soft-start
cycles after the 12V POR level has been surpassed. At time
t6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q
1
and Q
3
) that connect the
ATX rails to the 3.3V
DUAL
and 5V
DUAL
rails. The 5VDLSB pin
is actively pulled high, which will turn the P-MOSFET (Q
2
) off.
Finally, the internal LDO which regulates the 3.3V
AUX
rail in
sleep states is put in standby mode.
FIGURE 3. ISL6506 AND ISL6506B SOFT-START INTERVAL
IN S4/S5 STATE AND S5 TO S0 TRANSITION
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
0V
5VDLSB
(5V/DIV)
DLA
(10V/DIV)
t3
t4 t5
TIME
t6
t0
t1
t2
FIGURE 4. SOFT-START INTERVAL FOR ISL6506A IN S4/S5
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506, ISL6506A,
ISL650B
Sleep to Wake State Transitions
Figures 3 and 4, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506, ISL6506B from the S4/S5 state to
the S0 state. Figure 4 shows how the ISL6506, ISL6506B
will transition from the S3 sleep state into S0 state. Figure 3
also shows how the ISL6506A transitions from either S3 or
S4/S5 in the S0 state. For all transitions, t4 depicts the
system transition into the S0 state. Here, the ATX supplies
are enabled and begin to ramp up. At time t5, the 12V
ATX
rail
has exceeded the POR threshold for the ISL6506, ISL6506B
and ISL6506A. Three soft-start periods after time t5, at time
t6, three events occur simultaneously. The DLA pin is forced
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