BU-64703
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®
SIMPLE SYSTEM RT MARK3
(SSRT MARK3)
FEATURES
•
Complete Integrated Remote Terminal
Including:
•Dual Low-Power 3.3V or 5.0V
Transceivers
•Complete RT Protocol Logic
•
Supports MIL-STD-1553A/B Notice 2,
STANAG-3838 RT, and
MIL-STD-1760 Stores Management
•
World’s Smallest CQFP SSRT
•
80-Pin Ceramic Flat Pack or Gull Wing
Package
DESCRIPTION
The BU-64703 Simple System RT Mark3 (SSRT Mark3) MIL-
STD-1553 terminal provides a complete interface between a simple
system and a MIL-STD-1553 bus. The SSRT Mark3 can be powered
entirely by 3.3 volts, thus eliminating the need for a 5V power supply.
This terminal integrates dual transceiver, protocol logic, and a FIFO
memory for received messages in an extremely small, 0.88 inch
square 0.130” max height ceramic package. The gull wing package
with a “toe-to-toe” maximum dimension of 1.110 inches enables its
use in applications where PC board space is at a premium. The
SSRT Mark3 provides multi-protocol support of MIL-STD-1553A/B,
MIL-STD-1760, McAir, and STANAG-3838.
The SSRT Mark3's transceivers are completely monolithic, require
only a +3.3V supply (+5.0V available), and consume low power. The
internal architecture is identical to that of the original BU-61703/61705
Simple System RT (SSRT). There are versions of the Simple System
RT Mark3 available with transceivers trimmed for MIL-STD-1760
compliance, or compatible to McAir standards. The SSRT Mark3 can
operate with a choice of clock frequencies at 10, 12, 16, or 20 MHz.
The SSRT Mark3 incorporates a Built-In-Test (BIT). This BIT, which is
processed following power turn-on or after receipt of an Initiate Self-
Test Mode command, provides a comprehensive test of the SSRT
Mark3's encoders, decoders, protocol, transmitter watchdog timer,
and protocol section. The SSRT Mark3 also includes an auto-config-
uration feature.
The SSRT Mark3 is ideal for stores and other simple systems that do
not require a microprocessor. To streamline the interface to simple
systems, the SSRT Mark3 includes an internal 32-word FIFO for
received data words. This serves to ensure that only complete, con-
sistent blocks of validated data words are transferred to a system.
•
3.3V Logic Power
•
Meets 1553A/McAir Response Time
Requirements
•
Internal FIFO for Burst Mode Capability on
Receive Data
•
16-bit DMA Interface
•
Auto Configuration Capability
•
Comprehensive Built-In Self-Test
•
Direct Interface to Simple (Processorless)
Systems
•
Available with Full Military Temperature
Range and Screening
•
Selectable Input Clock:
10, 12, 16, or 20 MHz
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
©
2003 Data Device Corporation
+Vcc
TX/RX A
TRANSCEIVER
A
DTREQ
DTGRT
DTACK
HS FAIL
MEMOE
MEMWR
DATA
BUFFERS
D15-D0
Data Device Corporation
www.ddc-web.com
TX/RX A
SYSTEM
DATA
TX_INH
TX/RX B
TRANSCEIVER
B
TX/RX B
DMA
HANDSHAKE
AND
TRANSFER
CONTROL
LOGIC
DMA
HANDSHAKE
CONTROL
DATA
TRANSFER
CONTROL
MSTCLR
CONTROL
INPUTS
AUTO_CFG
BRO_ENA
L_BRO, T/R, SA4-SA0
WC/MC/CWC4-0
DUAL
ENCODER
DECODER
AND
RT STATE
LOGIC
COMMAND
ADDRESS
BUS
ILLEGAL
SRV_RQST
SSFLAG
BUSY
RTACTIVE
INCMD
GBR
MSG_ERR
RTFAIL
2
RTAD4-RTAD0
RT
ADDRESS
RTADP
RT_AD_LAT
RT
WORD
INPUTS
RT_AD_ERR
CLK_IN
CLK_SEL1
RT
MESSAGE
STATUS
CLOCK
FREQUENCY
SELECTION
CLK_SEL0
BU-64703
H-06/11-0
FIGURE 1. SSRT Mark3 BLOCK DIAGRAM
TABLE 1. SSRT Mark3 SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
•
Logic +3.3V
•
Transceivers +3.3V (Note 10)
(not during transmit)
•
Transceiver +3.3V
(during transmit) (Note 10)
•
Transceiver +5.0V
•
+3.3V Logic Input Range
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage (Note 8)
•
Direct Coupled Across 35
Ω,
Measured on Bus
•
Transformer Coupled Across
70
Ω,
Measured on Bus
BU-64703XX-XX0
BU-64703X8/3-XX2 (Note 9)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
BU-64703X8/3
BU-64703X9/4
LOGIC
V
IH
All signals except CLOCK_IN
CLOCK_IN
V
IL
All signals except CLOCK_IN
CLOCK_IN
Schmidt Hysteresis
All signals except CLOCK_IN
CLOCK_IN
I
IH
, I
IL
All signals except CLOCK_IN
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IH
=2.7V)
I
IL
(Vcc=3.6V, V
IH
=0.4V)
CLOCK_IN
I
IH
I
IL
V
OH
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
(Vcc = 3.0V)
I
OH
(Vcc = 3.0V)
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
MIN
TYP
MAX
UNITS
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
PARAMETER
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
•
+3.3V Logic
•
+3.3V Transceivers (Note 10)
•
+5.0V Transceivers
Current Drain(Total Hybrid)(Notes 8,14)
•
BU-64703X8/9-XX0,(1553 & McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-64703X8-XX2, (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Current Drain(Total Hybrid)(Notes 8,14)
•
BU-64703X3/4-X00,(1553 & McAir)
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
•
BU-64703X3-X02,(1760)
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
POWER DISSIPATION
Total Hybrid (Notes 8, 11 and 14)
•
BU-64703X8/9-XX0, (1553 & McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-64703X8-XX2, (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-64703X3/4-X00, (1553 & McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-64703X3-X02, (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
•
BU-64703X8/9-XX0 (1553 &McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-64703X8-XX2 (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
2.5
6.0
6.0
4.5
7.0
6.0
V
V
V
V
V
kΩ
3.00
3.14
4.75
3.3
3.3
5.0
3.60
3.46
5.25
95
300
500
900
95
315
535
975
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
5
0.200
0.860
10
pF
Vp-p
Vpeak
6
7
9
Vp-p
100
205
310
520
40
100
216
332
565
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
18
20
-250
100
200
20
21.5
27
27
10
250
Vp-p
Vp-p
mVp-p
mV
peak
nsec
nsec
150
250
300
300
2.1
0.8•Vcc
0.7
0.2•Vcc
0.4
1.0
-10
-350
-350
-10
-10
2.4
0.4
2.2
-2.2
50
50
10
-33
-33
10
10
V
V
V
V
V
V
µA
µA
µA
µA
µA
V
V
mA
mA
pF
pF
0.31
0.69
1.04
1.74
0.31
0.71
1.08
1.83
0.63
0.85
1.07
1.51
0.63
0.86
1.09
1.56
0.09
0.47
0.82
1.52
0.09
0.49
0.85
1.61
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Data Device Corporation
www.ddc-web.com
3
BU-64703
H-06/11-0
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
PARAMETER
POWER DISSIPATION (CONT’D)
•
BU-64703X3/4-X00 (1553 &McAir)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-64703X3-X02 (1760)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
CLOCK INPUT
Frequency
•
Nominal Value
• Default
• Option
• Option
• Option
•
Long Term Tolerance
TABLE 1. SSRT Mark3 SPECIFICATIONS (Cont’d)
PARAMETER
1553 MESSAGE TIMING
RT-to-RT Response Timeout
(Note 12)
RT Response Time
(mid-parity to mid-sync) (Note 12)
Transmitter Watchdog Timeout
THERMAL
Thermal Resistance (Notes 8, 13)
Ceramic Flatpack / Gull Lead
Junction-to-Case, Hottest Die (θ
JC
)
Operating Case Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
PHYSICAL CHARACTERISTICS
Size
80-pin Ceramic Flatpack / Gull Lead
Lead Toe-to-Toe Distance
80-pin Gull Wing
Weight
80-pin Ceramic Flatpack/Gull Wing
Package
MIN
TYP
MAX UNITS
MIN
TYP
MAX
UNITS
0.25
0.47
0.69
1.13
0.25
0.48
0.71
1.18
W
W
W
W
W
W
W
W
17.5
4
18.5
660.5
19.5
7
µs
µs
µs
9
-55
-40
0
-55
-65
11
+125
+85
+70
150
150
+300
°C/W
°C
°C
°C
°C
°C
°C
16.0
12.0
10.0
20.0
0.01
0.10
-0.001
-0.01
40
-0.01
-0.10
0.001
0.01
60
MHz
MHz
MHz
MHz
%
%
%
%
%
• 1553A Compliance
• 1553B Compliance
•
Short Term Tolerance, 1 second
0.88 X 0.88 X 0.13
(22.3 x 22.3 x 3.3)
1.110
(28.194)
0.353
(10)
in.
(mm)
in.
(mm)
oz
(g)
• 1553A Compliance
• 1553B Compliance
•
Duty Cycle
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance Specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Impedance parameters are specified directly between pins
TX/RX A(B) and
TX/RX A(B
) of the SSRT Mark3 hybrid.
(3) It is assumed that all power and ground inputs to the hybrid are con-
nected.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to the pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid-
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8) An "X" in one or more of the product type fields indicates that the
reference is applicable to all available product options.
(9) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con-
nection.
(10) External 10 µF tantalum and 0.1 µF capacitors to ground should be
located as close as possible to +3.3 Vdc input pins.
(11) Power dissipation is the input power minus the power delivered to
the 1553 fault isolation resistors, the power delivered to the bus ter-
mination resistors, and the copper losses in the transceiver isolation
transformer and the bus coupling transformer. An illustration of exter-
nal power dissipation for transformer coupled configuration (while
transmitting) is: 0.14 watts for the active isolation transformer, 0.08
watts for the active bus coupling transformer, 0.45 watts for each of
the two bus isolation resistors and 0.15 watts for each of the two bus
termination resistors.
(12) Measured from mid-parity crossing of command word to mid-sync
crossing of RT's status word.
(13)
θ
JC
is measured to bottom of ceramic case.
(14) Current drain and power dissipation specifications are based on a
small sample size and subject to change.
Data Device Corporation
www.ddc-web.com
4
BU-64703
H-06/11-0
INTRODUCTION
GENERAL
The BU-64703 Simple System RT Mark3 (SSRT Mark3) is a
complete MIL-STD-1553 Remote Terminal (RT) bus interface
unit. Contained in this hybrid are a dual transceiver and
Manchester II encoder/decoder, and MIL-STD-1553 Remote
Terminal (RT) protocol logic. Also included are built-in self-test
capability and a parallel subsystem interface. The subsystem
interface includes a 12-bit address bus and a 16-bit data bus that
operates in a 16-bit DMA handshake transfer configuration. The
local bus and associated control signals are optimized for +3.3
volt logic but are +5 volt tolerant.
The transceiver front end of the SSRT Mark3 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +3.3V voltage source (+5.0V available).
The voltage source transmitters provide superior line driving
capability for long cables and heavy amounts of bus loading. In
addition, the monolithic transceivers can provide a minimum stub
voltage level of 20 volts peak-to-peak transformer coupled, mak-
ing the SSRT Mark3 suitable for MIL-STD-1760 applications. To
provide compatibility to McAir specs, the SSRT Mark3 is avail-
able with an option for transmitters with increased rise and fall
times.
Besides eliminating the demand for an additional power supply,
the use of a +3.3V only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer. This provides the
advantage of a higher terminal input impedance than is possible
for a 15V, 12V or 5V transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553
validation test. This allows for longer cable lengths between a
system connector and the isolation transformers of an embed-
ded 1553 terminal.
The receiver sections of the SSRT Mark3 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The SSRT Mark3 implements all MIL-STD-1553 message for-
mats, including all 13 MIL-STD-1553 dual redundant mode
codes. Any subset of the possible 1553 commands (broadcast,
T/R bit, subaddress, word count/mode code) may be optionally
illegalized by means of an external PROM, PLD, or RAM. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined command word and correct word count. If the SSRT
Mark3 is the receiving RT in an RT-to-RT transfer, it verifies that
the T/R bit of the transmit command word is logic "1" and that the
transmitting RT responds in time and contains the correct RT
address in its Status Word.
The SSRT Mark3 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples
incoming data on
both
edges of the clock input. This oversam-
pling, in effect, provides for a sampling rate of twice the input
clocks' frequency. Benefits of the higher sampling rate include a
wider tolerance for zero-crossing distortion and improved bit
error rate performance.
The SSRT Mark3 includes a hardwired RT address input. This
includes 5 address lines, an address parity input, and an address
parity error output. The RT address can also be latched by
means of a latching input signal.
The SSRT Mark3 supports command illegalization. Commands
may be illegalized by asserting the input signal ILLEGAL active
low within approximately 2 µs after the mid-parity bit zero-cross-
ing of the received command word. Command words may be
illegalized as a function of broadcast, T/R bit, subaddress, word
count, and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The SSRT Mark3 provides a number of real-time output signals.
These various signals provide indications of message in prog-
ress, valid received message, message error, handshake fail,
loop-test fail or transmitter timeout.
The SSRT Mark3 includes standard DMA handshake sig-
nals (Request, Grant, and Acknowledge) as well as transfer
control outputs (MEMOE and MEMWR). The DMA interface
operates in a 16-bit mode, supporting word-wide transfers.
The SSRT Mark3's system interface allows the SSRT Mark3 to
be interfaced directly to a simple system that doesn't include a
microprocessor. This provides a low-cost 1553 interface for A/D
and D/A converters, switch closures, actuators, and other dis-
crete I/O signals.
The SSRT Mark3 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the SSRT Mark3 to
transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a rate
of one data word every three clock cycles. Burst mode negotiates
only once for use of the subsystem bus. Negotiation is performed
only after all 1553 data words have been received and validated. In
non-burst mode, the SSRT Mark3 will negotiate for the local bus
after every received data word. The data word transfer period is
three clock cycles for each received 1553 data word.
The SSRT Mark3 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a small amount
of "glue" logic, the SSRT Mark3 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a
shared RAM for each broadcast / T/R bit / subaddress / mode
code.
Data Device Corporation
www.ddc-web.com
5
BU-64703
H-06/11-0
FPGA/CPLD
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