K7A323600M
K7A321800M
Document Title
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
1. Initial draft
1. Add 165FBGA package
1. Update JTAG scan order
2. Speed bin merge.
From K7A3236(18)09M to K7A3236(18)00M.
3. AC parameter change.
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20
1. Change pin out for 165FBGA
- x18/x36 ; 11B => from A to NC , 2R ==> from NC to A .
1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change
- x18/x36 ; insert Pin ID of 2R to BIT number of 69
1. Add Icc, Isb,Isb1 and Isb2 values
1. Correct the pin name of 100TQFP.
1. Add the Industrial temperature range.
1. Change the Stand-by current (Isb)
Before
After
Isb - 25 : 120
170
- 22 : 110
160
- 20 : 100
150
- 16 :
90
140
- 15 :
90
140
- 14 :
90
140
Isb1
:
90
110
Isb2
:
80
100
1. Delete the 119BGA and 165FBGA package.
2. Delete the 225MHz, 167MHz and 150MHz speed bin
Draft Date
May. 10. 2001
Aug. 29. 2001
Dec. 31. 2001
Remark
Advance
Preliminary
Preliminary
0.3
Feb. 14. 2002
Preliminary
0.4
Apr. 20. 2002
Preliminary
0.5
1.0
1.1
1.2
May.10. 2002
Oct. 15. 2002
Mar. 19, 2003
Oct. 17, 2003
Preliminary
Final
Final
Final
2.0
Nov. 18, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov. 2003
Rev 2.0
K7A323600M
K7A321800M
1Mx36 & 2Mx18 Synchronous SRAM
1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A323600M and K7A321800M are 37,748,736-bit
Synchronous Static Random Access Memory designed for
high performance second level cache of Pentium and
Power PC based System.
It is organized as 1M(2M) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; G W, BW , LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by G W, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor(ADSP ) or address status cache control-
ler( ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system′s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A323600M and K7A321800M are fabricated using
SAMSUNG′s high performance CMOS technology and is
available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-25
4.0
2.6
2.6
-20
5.0
3.1
3.1
-14
7.2
4.0
4.0
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′
0
~A′
1
COUNTER
A
0
~A
1
A
0
~A
19
or A
0
~A
20
ADDRESS
REGISTER
A
2
~A
19
or A
2
~A
20
1Mx36 , 2Mx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
W
Ex
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-3-
Nov. 2003
Rev 2.0
FPGA/CPLD
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