NCP1255
Current-Mode PWM
Controller for Off-line
Power Supplies featuring
Peak Power Excursion
The NCP1255 is a highly integrated PWM controller capable of
delivering a rugged and high performance offline power supply in a
SOIC−8 package. With a supply range up to 35 V, the controller hosts a
jittered 65−kHz switching circuitry operated in peak current mode
control. When the power on the secondary side starts to decrease, the
controller automatically folds back its switching frequency down to a
minimum level of 26 kHz. As the power further goes down, the part
enters skip cycle while freezing the peak current setpoint.
To help build rugged converters, the controller features several key
protective features: a brown−out, a non−dissipative Over Power
Protection for a constant maximum output current regardless of the
input voltage, two latched over voltage protection inputs − either
through a dedicated pin or via the V
cc
input − and finally, the
possibility to externally adjust an auto−recovery timer duration.
The controller architecture is arranged to authorize a transient peak
power excursion when the peak current hits the limit. At this point, the
switching frequency is increased from 65 kHz to 130 kHz until the
peak requirement disappears. The timer duration is then modulated as
the converter crosses a peak power excursion mode (long) or
undergoes a short circuit (short).
Features
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8
1
SOIC−8
D1, D2 SUFFIX
CASE 751
MARKING DIAGRAM
8
1255x65
ALYW
G
1
1255x65 = Specific Device Code
x = A, B, C or D
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
65−kHz Fixed−frequency Current−mode Control Operation with
•
•
•
•
•
•
•
•
•
•
•
•
•
130−kHz Excursion
Internal and Adjustable Over Power Protection (OPP) Circuit
Adjustable Brown−Out Protection Circuit
Frequency Foldback down to 26 kHz and Skip−cycle in Light Load
Conditions
Adjustable Slope Compensation
Internally Fixed 4−ms Soft−start
Adjustable Timer−based Auto−recovery Overload/Short−circuit
Protection
100% to 25% Timer Reduction from Overload to Short−circuit Fault
Double V
cc
Hiccup for a Reduced Average Power in Fault Mode
Frequency Jittering in Normal and Frequency Foldback Modes
Latched OVP Input for Improved Robustness and Latched OVP on V
cc
Up to 35−V V
cc
Maximum Rating
Extremely Low No−load Standby Power
This is a Pb−Free Device
PIN CONNECTIONS
OPP/Latch
FB
CS
GND
1
2
3
4
(Top View)
8
7
6
5
Timer
BO
Vcc
DRV
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Typical Applications
•
Converters requiring peak−power capability such as printers power
supplies, ac−dc adapters for game stations.
©
Semiconductor Components Industries, LLC, 2015
1
September, 2015 − Rev. 2
Publication Order Number:
NCP1255/D
NCP1255
Vbulk
.
.
OVP
Vout
OPP
1
2
3 Eris
4
Eris
NCP1255
8
7
6
5
BO
.
ramp
comp.
Figure 1. Typical Application Example
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
1
Pin Name
OPP/OVP
Function
Adjust the Over Power Protection.
Latches off the part
Feedback pin
Current sense + ramp
compensation
−
Driver output
Supplies the controller
Brown−Out input
Sets the timer duration
Pin Description
A resistive divider from the auxiliary winding to this pin sets the
OPP compensation level. When brought above 3 V, the part is fully
latched off.
Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak current but also offers a means
to introduce ramp compensation.
The controller ground.
The driver’s output to an external MOSFET gate.
This pin is connected to an external auxiliary voltage and supplies
the controller. When above a certain level, the part fully latches off.
A voltage below the programmed level stops the controller. When
above, the controller can start.
A 22−kW resistor sets the duration to 200 ms. When shorted to
ground or made open, this pin limits the internal current and fixes
the timer duration.
2
3
4
5
6
7
8
FB
CS
GND
DRV
V
cc
BO
Timer
Table 2. ORDERING INFORMATION AND OPTIONS
Controller
NCP1255AD65R2G
NCP1255BD65R2G
NCP1255CD65R2G
NCP1255DD65R2G
Frequency
65 kHz
65 kHz
65 kHz
65 kHz
OCP Latched
Yes
No
Yes
No
OCP Auto−Recovery
No
Yes
No
Yes
V
BOoff
(V)
0.6
0.6
0.7
0.7
SOIC−8
(Pb−Free)
2500 / Tape
& Reel
Package
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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2
NCP1255
OPP
600−ns time
constant
Vlatch
OVP
gone?
Up counter
RST
4
S
Vcc and logic
management
double hiccup
Vdd
power
VOVP on reset
UVLO
Vcc
Vref
100% to
25% change
SC
Upper
/ lower
limit
Timer
Vcc
20
ms
option
latch/AR
Q
Q
1−ms
blanking
Rlimit
IpFlag, PON reset
Vcc
R
Power on
reset
Jitter mod.
BO
BO
65 kHz
clock
S
Clamp
VBO1
VBO2
Frequency
increase to
130 kHz
VFswp
Vskip
Vfold
Frequency
foldback
Q
Q
R
Drv
Rramp
vdd
SC
RFB
/4
FB
VOPP
250 mV
peak current
freeze
+
VSC
The soft−start is
Ip flag
activated during:
− the startup sequence
− the auto−recovery burst mode
VFB < 1 V ? setpoint = 250 mV
Vlimit + VOPP
4 ms
SS
CS
LEB
GND
Vlimit
Figure 2. Internal Circuit Architecture
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3
NCP1255
Table 3. MAXIMUM RATINGS TABLE
Symbol
V
cc
Rating
Power Supply voltage, V
cc
pin, continuous voltage
Maximum voltage on low power pins CS, FB, Timer, OPP and BO
V
DRV
IOPP
I
SCR
R
θJ−A
T
J,max
T
STG
HBM
MM
CDM
Maximum voltage on drive pin
Maximum injected current into the OPP pin
Maximum continuous current into the V
cc
pin while in latched mode
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
Human Body Model ESD Capability (All pins except HV) per JEDEC JESD22−A114F
Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
Value
−0.3 to 35
−0.3 to 10
−0.3 to V
cc
+0.3
−2
3
178
150
−60 to +150
2
200
500
Unit
V
V
V
mA
mA
°C/W
°C
°C
kV
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
= −40°C to +125°C, Max T
J
= 150°C, V
cc
= 12 V unless otherwise noted)
Symbol
SUPPLY SECTION
VCC
ON
VCC
(min)
VCC
HYST
V
ZENER
ICC1
ICC2
ICC3
ICC4
ICC5
ICCstby
ICC
LATCH
R
lim
V
CC
increasing level at which driving pulses are authorized
V
CC
decreasing level at which driving pulses are stopped
Hysteresis Vcc
ON
−Vcc
(min)
Clamped V
cc
when latched off @ ICC = 500
mA
Start−up current
Internal IC consumption with V
FB
= 3.2 V, F
SW
= 65 kHz and C
L
= 0
Internal IC consumption with V
FB
= 3.2 V, F
SW
= 65 kHz and C
L
= 1 nF
Internal IC consumption with V
FB
= 4.5 V, F
SW
= 130 kHz and C
L
= 0
Internal IC consumption with V
FB
= 4.5 V, F
SW
= 130 kHz and C
L
= 1 nF
Internal IC consumption while in skip mode
(V
cc
= 12 V, driving a typical 6−A/600−V MOSFET)
Current flowing into V
CC
pin that keeps the controller latched:
T
j
= −40°C to 125°C
SCR current−limit series resistor
6
6
6
6
6
6
6
6
6
6
6
40
6
4
kW
15.8
8
6
−
−
−
−
−
−
18
8.8
−
7
−
1.4
2.1
1.7
3.1
750
20
9.4
−
−
15
2.2
3.0
2.5
4.0
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
Rating
Pin
Min
Typ
Max
Unit
DRIVE OUTPUT
T
r
T
f
R
OH
R
OL
I
source
I
sink
V
DRVlow
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
Source resistance
Sink resistance
Peak source current, V
GS
= 0 V – (Note 2)
Peak sink current, V
GS
= 12 V – (Note 2)
DRV pin level at V
CC
close to VCC
(min)
with a 33−kW resistor to GND
5
5
5
5
5
5
5
8
−
−
−
−
40
30
13
6
300
500
−
−
−
−
−
−
ns
ns
W
W
mA
mA
V
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 3 below −300 mV.
4. A 1−MW resistor is connected from pin 3 to the ground for the measurement.
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NCP1255
Table 4. ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
= −40°C to +125°C, Max T
J
= 150°C, V
cc
= 12 V unless otherwise noted)
Symbol
DRIVE OUTPUT
V
DRVhigh
DRV pin level at V
CC
= V
OVP
−0.2 V – DRV unloaded
5
10
12
14
V
Rating
Pin
Min
Typ
Max
Unit
CURRENT COMPARATOR
I
IB
V
Limit1
V
Limit2
V
foldI
V
freezeI
T
DEL
T
LEB
TSS
IOPPo
IOOPv
IOOPv
IOPPs
Input Bias Current @ 0.8 V input level on pin 3
Maximum internal current setpoint – Tj = 25°C – pin1 grounded
Maximum internal current setpoint – Tj from −40° to 125°C –
pin 1 grounded
Default internal voltage set point for frequency foldback trip point
≈
59% of V
limit
Internal peak current setpoint freeze (≈31% of V
limit
)
Propagation delay from current detection to gate off−state
Leading Edge Blanking Duration
Internal soft−start duration activated upon startup, auto−recovery
Setpoint decrease for pin 3 biased to –250 mV – (Note 3)
Voltage setpoint for pin 1 biased to −250 mV – (Note 3), T
j
= 25°C
Voltage setpoint for pin 1 biased to −250 mV – (Note 3),
T
j
from −40° to 125°C
Setpoint decrease for pin 1 grounded
3
3
3
3
3
3
3
−
3
3
3
3
0.51
0.5
0.744
0.72
0.02
0.8
0.8
475
250
100
300
4
31.3
0.55
0.55
0
0.6
0.62
150
0.856
0.88
mA
V
V
mV
mV
ns
ns
ms
%
V
V
%
INTERNAL OSCILLATOR
f
OSC,nom
V
FBtrans
f
OSC,max
V
FBmax
D
max
f
jitter
f
swing
Oscillation frequency, V
FB
< V
Fbtrans
, pin 1 grounded
Feedback voltage above which F
sw
increases
Maximum oscillation frequency for V
FB
above V
FBmax
Feedback voltage above which F
sw
is constant
Maximum duty ratio
Frequency jittering in percentage of f
OSC
Swing frequency over the whole frequency range
−
−
−
−
−
−
−
120
3.8
76
61
65
3.2
130
4.1
80
±5
240
140
4.2
84
71
kHz
V
kHz
V
%
%
Hz
FEEDBACK SECTION
R
up
R
eq
I
ratio
V
freezeF
Internal pull−up resistor
Equivalent ac resistor from FB to gnd
Pin 2 to current setpoint division ratio
Feedback voltage below which the peak current is frozen
2
2
−
2
15
13
4
1
V
kW
kW
FREQUENCY FOLDBACK
V
foldF
F
trans
V
fold,end
V
skip
Skip
hysteresis
Frequency foldback level on the feedback pin –
≈59%
of maximum peak current
Transition frequency below which skip−cycle occurs
End of frequency foldback feedback level, F
sw
= F
min
Skip−cycle level voltage on the feedback pin
Hysteresis on the skip comparator – (Note 2)
−
−
−
−
22
1.9
26
1.5
400
30
30
V
kHz
V
mV
mV
INTERNAL SLOPE COMPENSATION
V
ramp
Internal ramp level @ 25°C – (Note 4)
3
2.5
V
2. Guaranteed by design
3. See characterization table for linearity over negative bias voltage – we recommend keeping the level on pin 3 below −300 mV.
4. A 1−MW resistor is connected from pin 3 to the ground for the measurement.
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