DLR3416
HIGH EFFICIENCY RED
DLO3416
GREEN
DLG3416
RED
.270" 4-character 5 x 7 Dot Matrix
Alphanumeric Intelligent Display
with Memory/Decoder/Drive
Dimensions in inches (mm)
.157 (.40)
±.007
(.18)
.325
(8.26)
.175
(4.45)
.260 (6.60)
±.007
(.18)
.790
(20.07)
±.010
(.25)
.270
(6.86)
1.300 (33.02) max
.600 (15.24)
±.020
(.51)
at Seating
Plane
Pin 1
Indicator
EIA Date Code
DLX3416
SIEMENS
Z
YYWW
Luminous
Intensity Code
340 (8.64)
.160 (4.06)
±.020
(.51)
Part
No.
FEATURES
• Dot Matrix Replacement for DL3416
• 0.270" 5x7 Dot Matrix Characters
• 128 Special ASCII Characters for English,
German, Italian, Swedish, Danish, and Norwe-
gian Languages
• Wide Viewing Angle: X Axis 50
°
Maximum,
Y Axis
±
75
°
Maximum
• Close Vertical Row Spacing, 0.800" Centers
• Fast Access Time, 110 ns at 25
°
C
• Full Size Display for Stationary Equipment
• Built-in Memory
• Built-in Character Generator
• Built-in Multiplex and LED Drive Circuitry
• Each Character Independently Accessed
• TTL Compatible, 5 Volt Power, V
IH
=2.0 V,
V
IL
=0.8 V
• Independent Cursor Function
• Memory Clear Function
• Display Blank Function for Blinking and Dim-
ming
• End-Stackable, 4-character Package
• Intensity Coded for Display Uniformity
• Extended Operating Temperature Range:
–40
°
C to +85
°
C
• Wave Solderable
See Appnotes 18, 19, 22, and 23 for additional
information.
.145 (3.68)
±.015
(.38)
at Seating Plane
.100 (2.54)
±.015
(38)
at Seating Plane
.020 (.51) x .012(.30)
Leads 22 pl.
DESCRIPTION
The DLR/DLO/DLG3416 is a four character 5x7 dot matrix display module
with a built-in CMOS integrated circuit. This display is a “drop-in” replace-
ment for the DL3416.
The integrated circuit contains memory, ASCII ROM decoder, multiplexing
circuitry and drivers. Data entry is asynchronous and can be random. A dis-
play system can be built using any number of DLX3416s since each charac-
ter can be addressed independently and will continue to display the
character last stored until replaced by another.
System interconnection is very straightforward. The least significant two
address bits (A0, A1) are normally connected to the like-named inputs of all
displays in the system. With four chip enables, four displays (16 characters)
can easily be interconnected without a decoder.
Data lines are connected to all DLX3416s directly and in parallel, as is the
write line (WR). The display will then behave as a write-only memory.
The cursor function causes all dots of a character position to illuminate at
half brightness. The cursor is not a character, and when removed the previ-
ously displayed character will reappear.
The DLX3416 has several features superior to competitive devices. True
“blanking” allows the designer to dim the display for more flexibility of dis-
play presentation. Finally the CLR clear function will clear the cursor RAM
and the ASCII character RAM simultaneously.
The character set consists of 128 special ASCII characters for English, Ger-
man, Italian, Swedish, Danish, and Norwegian.
All products are subjected to out-going AQL’s of 0.25% for brightness match-
ing, visual alignment and dimensions, 0.065% for electrical and functional.
2–1
Maximum Ratings
DC Supply Voltage .................... –0.5 V to +7.0 Vdc
Input Voltage, Respect to GND
(all inputs) .......................–0.5 V to V
CC
+0.5 Vdc
Operating Temperature .................. -40
°
C to +85
°
C
Storage Temperature-.................... 40
°
C to +100
°
C
Relative Humidity at 85
°
C
(non-condensing) .........................................85%
Maximum Solder Temperature,
0.063" (1.59 mm) below
Seating Plane, t<5 sec ............................. 260
°
C
Optical Characteristics
Spectral Peak Wavelength
Red .................................................. 660 nm typ.
HER .................................................. 630 nm typ.
Green ............................................... 565 nm typ.
Character Height0.270" (6.86 mm)
Time Averaged Luminous Intensity(1)
at V
CC
=5 V
Red ............................................ 60
µ
cd/LED typ.
HER.......................................... 120
µ
cd/LED typ.
Green ....................................... 140
µ
cd/LED typ.
Dot to Dot Intensity Matching
at V
CC
=5 V ....................................... 1.8:1.0 max.
LED to LED Hue Matching
(Green only) at V
CC
=5 V ...................
±
2 nm max.
Viewing Angle (off normal axis)
Horizontal ...........................................
±
50
°
max.
Vertical . .............................................
±
75
°
max.
Note 1: Peak luminous intensity values can be calculated
by multiplying these values by 7.
Figure 1. Top view
22 21 20 1918 17 16 15 14 13 12
digit 3 digit 2
digit 1 digit 0
1 2 3 4 5 6 7 8 9 10 11
Pin
1
2
3
4
5
6
7
8
9
10
11
Function
CE1 Chip Enable
CE2 Chip Enable
CE3 Chip Enable
CE4 Chip Enable
CLR Clear
V
CC
A0 Digit Select
A1 Digit Select
WR Write
CU Cursor Select
CUE Cursor Select
Pin
12
13
14
15
16
17
18
19
20
21
22
Function
GND
NC
BL Blanking
NC
D0 Data Input
D1 Data Input
D2 Data Input
D3 Data Input
D4 Data Input
D5 Data Input
D6 Data Input
Figure 2. Timing characteristics, Write Cycle waveforms
CE1, CE2
CE3, C34
CU, CLR
2.0 V
0.8 V
Tces
Tcus
Tclrd
Tas
Tah
Tceh
Tcuh
A0, A1
2.0 V
0.8 V
2.0 V
0.8 V
Tds
Tdh
2.0 V
0.8 V
TW
Tacc
D0-D6
WR
Note: These waveforms are not edge triggered.
DC Characteristics
Parameter
Min.
I
CC
80 dots on
I
CC
Cursor
I
CC
Blank
I
IL
(all inputs)
V
IH
(all inputs)
V
IL
(all inputs)
V
CC
4.5
5.0
30
2.0
0.8
5.5
4.5
5.0
2.8
60
–40
°
C
Typ.
150
Max.
190
170
4.0
120
25
2.0
0.8
5.5
4.5
5.0
2.3
50
Min.
+25
°
C
Typ.
135
Max.
165
140
3.0
100
20
2.0
0.8
5.5
2.0
40
Min.
+55
°
C
Typ.
118
Max.
150
125
2.5
80
mA
mA
mA
µ
A
V
V
V
V
CC
=5 V
V
CC
=5 V
V
CC
=5 V, BL=0.8 V
V
IN
=0.8 V, V
CC
=5 V
V
CC
=5 V
V
CC
=5 V
Units
Conditions
DLR/DLO/DLG3416
2–2
AC Characteristics
Guaranteed Minimum Timing Parameters at
V
CC
=5.0 V
±
0.5 V
Parameter
Chip Enable Set Up Time
Address Set Up Time
Cursor Set Up Time
Chip Enable Hold Time
Address Hold Time
Cursor Hold Time
Clear Disable Time
Write Time
Data Set Up Time
Data Hold Time
Clear Time
Access Time
Symbol
T
CES
T
AS
T
CUS
T
CEH
T
AH
T
CUH
T
CLRD
T
W
T
DS
T
DH
T
CLR
T
ACC
–40
°
C
0
10
10
0
20
20
1
60
20
20
1
90
+25
°
C
0
10
10
0
30
30
1
70
30
30
1
110
+85
°
C
0
10
10
0
40
40
1
90
50
40
1
140
Units
ns
ns
ns
ns
ns
ns
µ
s
ns
ns
ns
µ
s
ns
Data entry may be asynchronous and random. Digit 0
is defined as right hand digit with A1=A2=0.
To clear the entire internal four-digit memory hold the
clear (CLR) low for 1
µ
s. All illuminated dots will be
turned off within one complete display multiplex cycle,
1 msec minimum. The clear function will clear both the
ASCII RAM and the cursor RAM.
Loading Cursor
Setting the chip enables (CE1, CE2, CE3, CE4) and
cursor select (CU) to their true state will enable cursor
loading. A write (WR) pulse will now store or remove a
cursor into the digit location addressed by A0, A1, as
defined in data entry. A cursor will be stored if D0=1
and will removed if D0=0. The cursor (CU) pulse width
should not be less than the write (WR) pulse or errone-
ous data may appear in the display.
If the cursor is not required, the cursor enable signal
(CUE) may be tied low to disable the cursor function.
For a flashing cursor, simply pulse CUE. If the cursor
has been loaded to any or all positions in the display,
then CUE will control whether the cursor(s) or the
characters will appear. CUE does not affect the con-
tents of cursor memory.
Note: 1. T
ACC
=Set Up Time + Write Time + Hold Time.
Loading Data
Setting the chip enable (CE1, CE2, CE3, CE4) to their true state will
enable loading. The desired data code (D0-D6) and digit address (A0,
A1) must be held stable during the write cycle for storing new data.
Typical Loading Data State Table
BL
H
H
H
H
H
H
H
H
H
H
L
H
H
H
CE1
X
L
X
X
X
X
H
H
H
H
X
H
X
H
CE2
X
X
L
X
X
X
H
H
H
H
X
H
X
H
CE3
X
X
X
H
X
X
L
L
L
L
X
L
X
L
CE4
X
X
X
X
H
X
L
L
L
L
X
L
X
L
CUE
L
L
L
L
L
L
L
L
L
L
X
L
L
L
CU
X
X
X
X
X
X
H
H
H
H
X
H
X
H
WR
H
X
X
X
X
H
L
L
L
L
H
L
X
L
CLR
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
X
X
X
X
L
L
H
H
X
H
X
X
X
X
X
X
L
H
L
H
X
H
X
A1
A0
D6
D5
D4
D3
D2
D1
D0
Digit
3
G
G
G
G
G
G
G
G
G
B
G
2
R
R
R
R
R
R
R
R
L
L
L
1
E
E
E
E
E
E
E
U
U
U
U
0
Y
Y
Y
Y
Y
Y
E
E
E
E
E
previously loaded display
X
X
X
X
X
H
H
H
L
L
L
X
X
X
X
X
L
L
L
L
X
X
X
X
X
L
H
L
L
X
X
X
X
X
L
L
X
X
X
X
X
H
H
X
X
X
X
X
L
L
X
X
X
X
X
H
H
L
L
H
H
H
L
L
L
H
blank display
H
L
L
L
H
clears character display
see character code
see character set
X=don’t care
Loading Cursor State Table
BL
H
H
H
H
H
H
H
H
H
H
CE1
X
X
H
H
H
H
H
X
H
X
CE2
X
X
H
H
H
H
H
X
H
X
CE3
X
X
L
L
L
L
L
X
L
X
CE4
X
X
L
L
L
L
L
X
L
X
CUE
L
H
H
H
H
H
H
L
L
H
CU
X
X
L
L
L
L
L
X
L
X
WR
H
H
L
L
L
L
L
H
L
H
CLR
H
H
H
H
H
H
H
H
H
H
A1
A0
D6
D5
D4
D3
D2
D1
D0
Digit
3
B
B
B
B
B
s
s
B
B
B
2
E
E
E
E
s
s
E
E
E
E
1
A
A
A
s
s
s
s
A
A
s
0
R
R
s
s
s
s
s
R
R
s
L
L
H
H
H
H
previously loaded display
display previously stored cursors
L
X
X
X
X
X
H
X
X
X
X
X
L
X
X
X
X
X
H
X
X
X
X
X
L
H
L
L
L
H
disable cursor display
H
X
X
X
X
X
display stored cursors
X
X
X
X
L
X
H
H
H
H
L
L
X=don’t care
s
=all dots on
DLR/DLO/DLG3416
2–3
Display Blanking
Blank the display by loading a blank or space into each digit of
the display or by using the (BL) display blank input.
Setting the (BL) input low does not affect the contents of either
data or cursor memory. A flashing display can be achieved by
pulsing (BL). A flashing circuit can be constructed using a 555
a stable multivibrator. Figure 3 illustrates a circuit in which vary-
ing R2 (100K~10K) will have a flash rate of 1 Hz~10 Hz.
Figure 3. Flashing circuit using a 555
VCC=5.0 V
The display can be dimmed by pulsing (BL) line at a frequency
sufficiently fast to not interfere with the internal clock. The dim-
ming signal frequency should be 2.5 KHz or higher. Dimming
the display also reduces power consumption.
An example of a simple dimming circuit using a 556 is illus-
trated in Figure 4. Adjusting potentiometer R3 will dim the dis-
play by changing the blanking pulse duty cycle.
Figure 4. Flashing circuit using a 555
VCC=5.0 V
1
1
2
3
To BL
Pin on
Display
4
555
Timer
8
7
6
5
C4
0.01
µF
R2
100 KΩ
C3
10
µF
To BL
Pin on
Display
R1
4.7 KΩ
2
3
4
555
Timer
8
7
6
5
C4
0.01
µF
R1
4.7 KΩ
R2
100 KΩ
C3
10
µF
Figure 4a. Flashing (blanking) timing
1
0
Blanking Pulse Width
≈50%
Duty Factor
Blanking Pulse Width
≈50%
Duty Factor
~
500 ms
~
~
2 Hz Blanking Frequency
~
Figure 3a. Flashing (blanking) timing
1
0
~
500 ms
~
~
2 Hz Blanking Frequency
~
Figure 5. Internal block diagram
Display
Rows 0 to 6
3
Row Control Logic
&
Row Drivers
2
1
0
Columns 0 to 19
BL
OSC
÷
128
Counter
÷
7
Counter
Timing and Control Logic
RAM Read Logic
D6
D5
D4
D3
D2
D1
D0
Column Decoder
Row Decoder
Latches
7 Bit ASCII Code
ROM
128 X 35 Bit
ASCII
Character
Decode
4480 bits
Column Data
RAM
Memory
4 X 7 bit
Address Lines
Column Enable
Latches and
Column Drivers
Cursor
Memory
4 X 1 bit
Cursor Memory Bits 0 to 3
WR
A0
A1
Write
Address
Decoder
CUE
DLR/DLO/DLG3416
2–4
Character Set
D0
D1
D2
D3
D6 D5 D4 HEX
ASCII
CODE
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
1. High=1 level. 2. Low=0 level. 3. Upon power up, device will initialize in a random state.
Figure 6. Typical schematic, 16-character system
+V
GND
D15
CE1
CE2
D12 D11
CE3
CE4
CE1
CE2
CE3
D8 D7
CE1
CE2
CE3
CE4
D4 D3
CE4
CE1
CE2
CE3
D0
CE4
BL
D0-DL
CLR
WR
7
14
GND
GND
GND
CUE
A1
A0
A3
A2
GND
+V
+V
+V
+V
CU
DLR/DLO/DLG3416
2–5
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