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MT58L64V32FF-7.5

Description
Standard SRAM, 64KX32, 7.5ns, CMOS, PBGA165, FBGA-165
Categorystorage    storage   
File Size484KB,25 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT58L64V32FF-7.5 Overview

Standard SRAM, 64KX32, 7.5ns, CMOS, PBGA165, FBGA-165

MT58L64V32FF-7.5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeBGA
package instructionFBGA-165
Contacts165
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Maximum access time7.5 ns
Maximum clock frequency (fCLK)113 MHz
I/O typeCOMMON
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width32
Number of functions1
Number of terminals165
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
power supply2.5,3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.01 A
Minimum standby current3.14 V
Maximum slew rate0.245 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width13 mm
2Mb: 128K x 18, 64K x 32/36
FLOW-THROUGH SYNCBURST SRAM
2Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• 165-pin FBGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L128L18F, MT58L64L32F,
MT58L64L36F; MT58L128V18F,
MT58L64V32F, MT58L64V36F
3.3V V
DD
, 3.3V or 2.5V I/O, Flow-Through
100-Pin TQFP*
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
• Timing (Access/Cycle/MHz)
6.8ns/8.0ns/125 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
• Configurations
3.3V I/O
128K x 18
64K x 32
64K x 36
2.5V I/O
128K x 18
64K x 32
64K x 36
• Packages
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Part Number Example:
MARKING
-6.8
-7.5
-8.5
-10
MT58L128L18F
MT58L64L32F
MT58L64L36F
MT58L128V18F
MT58L64V32F
MT58L64V36F
T
F
None
*JEDEC-standard MS-026 BHA (LQFP).
GENERAL DESCRIPTION
The Micron
®
SyncBurst
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
MT58L64L36FT-8.5*
*See page 24 for the FBGA Part Marking Guide
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_2.p65 – Rev. 8/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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