EEWORLDEEWORLDEEWORLD

Part Number

Search

PT7V4050GACHB35.328/12.500

Description
PLL/Frequency Synthesis Circuit,
CategoryAnalog mixed-signal IC    The signal circuit   
File Size156KB,7 Pages
ManufacturerPericom Technology Inc
Download Datasheet Parametric View All

PT7V4050GACHB35.328/12.500 Overview

PLL/Frequency Synthesis Circuit,

PT7V4050GACHB35.328/12.500 Parametric

Parameter NameAttribute value
Is SamacsysN
Objectid106671795
package instructionSON, SLCC16,.4,100
Reach Compliance CodeUnknown
Analog Integrated Circuits - Other TypesPHASE LOCKED LOOP
Nominal supply voltage (Vsup)5 V
surface mountYES
JESD-30 codeR-PDSO-N16
width10.16 mm
length20.32 mm
Maximum seat height4.15 mm
Number of functions1
Maximum supply current (Isup)60 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Terminal pitch2.54 mm
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Terminal formNO LEAD
Number of terminals16
encapsulated codeSON
Encapsulate equivalent codeSLCC16,.4,100
Terminal locationDUAL
Maximum operating temperature70 °C
Minimum operating temperature
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
PLL with quartz stabilized VCXO
Loss of signals alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 65 Mb/s
Tri-state output
User defined PLL loop response
NRZ data compatible
Single +5.0V power supply
Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported: 12.000~50.000 MHz.
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
Loss Of Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPN
Op
Amp
OPOUT
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recoverymodule
PackageLeads
T: Thru-Hole
G: Surface Mount
CLK2 Divider
A: Divide by 2 E: Divide by 32
B: Divide by 4 F: Divide by 64
C: Divide by 8 G: Divide by 128
D: Divide by 16 H: Divide by 256
K: Disable
T
B
C
G
A
49.408 / 12.352
CLK2 Frequency
CLK1 Frequency
A: 5.0V supply voltage
B: 3.3V supply voltage
C:
±
20ppm
F:
±
32ppm
G:
±
50ppm
H:
±
100ppm
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
12.000
16.128
18.432
22.579
28.000
34.368
44.736
Frequencies using at CLK1 (MHz)
12.288
12.624
13.00
16.384
16.777
16.896
18.936
20.000
20.480
24.576
24.704
25.000
30.720
32.000
32.768
38.880
40.000
41.2416
47.457
49.152
49.408
19.440
35.328
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
Note:
CLK1 up to 40.960MHz for both 5V and
3.3V for temperature -40oC to 85 oC; CLK1 up to
50MHz for both 5V and 3.3V for temperature 0oC to 70oC.
PT0125(02/06)
1
Ver:2
How to write programs for MSP430 PWM with different frequencies
How to use MSP430 to make PWM waves of different frequencies? Please help me, experts....
ajungle Microcontroller MCU
EEWORLD University Hall----Live Replay: Application of MSP430 in Stepper Motor
Live replay: Application of MSP430 in stepper motor : https://training.eeworld.com.cn/course/27320...
hi5 Integrated technical exchanges
How to use C language to write high-quality code for MSP430
How to use C language to write high-quality code for MSP430...
wangshuzheng PCB Design
Data left and right shift problem for beginners
I have never been able to figure this out, I hope someone who knows can help me answer this question For example, when writing a byte in IIC or DS1302, the data must be shifted left and right. I don't...
Learner_new 51mcu
How to set the circuit diagram and PCB size in Protel 99 SE?
I am drawing a circuit diagram in Protel 99 SE. Because the drawing is very simple and small, the default size is too large. Wouldn't it be too large when making a printed circuit board later? Haha, s...
lddzp FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 922  676  2572  2356  2650  19  14  52  48  54 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号