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500DSAD200M000ABFR

Description
Oscillator, 0.9MHz Min, 200MHz Max, 200MHz Nom
CategoryPassive components    oscillator   
File Size92KB,4 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance
Download Datasheet Parametric View All

500DSAD200M000ABFR Overview

Oscillator, 0.9MHz Min, 200MHz Max, 200MHz Nom

500DSAD200M000ABFR Parametric

Parameter NameAttribute value
Is it Rohs certified?Yes
Objectid110358500
Reach Compliance CodeUnknown
Is SamacsysN
YTEOL0
Si500D
D
IFFERENTIAL
O
UTPUT
S
I L I C O N
O
SCILLATOR
Features
Quartz-free silicon oscillator
Any-rate output frequencies from 0.9 to 200 MHz
Quick turn delivery
Highly reliable startup and operation
Tri-state or power down operation
1.8, 2.5, or 3.3 V options
LVPECL, LVDS, HCSL, differential CMOS,
and differential SSTL versions available
3.2 x 4.0 mm footprint compatible with
industry-standard 3.2 x 5.0 mm pinout
Low power
Pb-free and RoHS compliant
Specifications
Parameters
Frequency Range
Frequency Stability
Operating Temperature
Storage Temperature
Supply Voltage
Condition
See Note 1.
Min
0.9
0
–55
1.71
2.25
2.97
46 – 13 ns/T
CLK
V
DD
– 1.5
.720
.68
1.15
0.25
0.85
0.25
0.35
0.65
45
V
DD
– 0.6
.5 x V
DD
+ 0.375
.5 x V
DD
+ 0.48
.45 x V
DD
+ 0.48
Typ
34.0
19.3
14.9
25.3
29.0
24.5
24.3
22.2
9.7
1.0
1.1
N/A
1
1
0.6
0.7
Max
200
±150
+70
+125
1.98
2.75
3.63
36.0
22.2
16.5
29.3
31.8
27.7
26.7
25
10.7
1.9
54 + 13 ns/T
CLK
460
800
1.6
V
DD
– 1.34
.880
.95
1.26
0.45
0.96
0.45
.425
.82
55
0.6
.5 x V
DD
– 0.375
.5 x V
DD
– 0.48
.45 V
DD
– 0.48
2
250 + 3 x T
CLK
250 + 3 x T
CLK
12 + 3 x T
CLK
2
2
3
1
1.5
Units
MHz
ppm
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
%
ps
ps
ns
V
V
PK
V
V
PK
V
V
PK
V
V
PK
V
V
PK
Ω
V
V
V
V
V
ms
ns
ns
µs
ms
ps RMS
ps RMS
ps RMS
ps RMS
Supply Current
Output Symmetry
Rise and Fall Times (20/80%)
2
LVPECL Output Option
(DC coupling, 50
Ω
to V
DD
– 2.0 V)
2
Low Power LVPECL Output Option
(AC coupling, 100
Ω
Differential Load)
2
LVDS Output Option (2.5/3.3 V)
(R
TERM
= 100
Ω
diff)
2
LVDS Output Option (1.8 V)
(R
TERM
= 100
Ω
diff)
2
HCSL Output Option
2
CMOS Output Voltage
2
SSTL Output Voltage
2
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped Mode
Return From Tri-State Time
Return From Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
1.8 V option
2.5 V option
3.3 V option
LVPECL
Low Power LVPECL
LVDS
HCSL
Differential CMOS(3.3 V option,10 pF,200 MHz)
Differential SSTL-3
Differential SSTL-2
Differential SSTL-18
Tri-State
Powerdown
V
DIFF
= 0
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
DC termination per pad
V
OH
, sourcing 9 mA
V
OL
, sinking 9 mA
SSTL-18
SSTL-2
SSTL-3
From time V
DD
crosses min spec supply
Non-CMOS
CMOS, C
L
= 7 pF
1.0 MHz – min(20 MHz, 0.4 x F
OUT
),non-CMOS
1.0 MHz – min(20 MHz, 0.4 x F
OUT
),CMOS format
Notes:
1.
Inclusive of 25 C° initial frequency accuracy, operating temperature range, supply voltage change, output load change, 1st year aging at
25 C°, shock and vibration.
2.
See AN409 for further details regarding output clock termination recommendations. SSTL minimum output voltage is minimum V
OH
. SSTL
maximum output voltage is maximum V
OL
.
Rev. 0.2 9/08
Copyright © 2008 by Silicon Laboratories
Si500D
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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