NXP Semiconductors
Data Sheet: Product Preview
Document Number S32K1XX
Rev. 3, 03/2017
S32K1xx Data Sheet
Key Features
• Operating characteristics
– Voltage range: 2.7 V to 5.5 V
– Ambient temperature range: -40 °C to 105 °C for
HSRUN, -40 °C to 125 °C for RUN
• ARM™ Cortex-M4F/M0+ core, 32-bit CPU
– Supports up to 112 MHz frequency with 1.25
Dhrystone MIPS per MHz
– ARM Core based on the ARMv7 Architecture and
Thumb®-2 ISA
– Integrated Digital Signal Processor (DSP)
– Configurable Nested Vectored Interrupt Controller
(NVIC)
– Single Precision Floating Point Unit (FPU)
• Clock interfaces
– 4 - 40 MHz fast external oscillator (SOSC)
– 48 MHz Fast Internal RC oscillator (FIRC)
– 8 MHz Slow Internal RC oscillator (SIRC)
– 128 kHz Low Power Oscillator (LPO)
– Up to 112 MHz System Phased Lock Loop (SPLL)
– Up to 50 MHz DC external square wave input clock
– Real Time Counter (RTC)
• Power management
– Low-power ARM Cortex-M4F/M0+ core with
excellent energy efficiency
– Power Management Controller (PMC) with multiple
power modes: HSRUN, Run, Stop, VLPR, and
VLPS
– Supports peripheral specific clock gating. Only
specific peripherals remain working in low power
modes.
• Memory and memory interfaces
– Up to 2 MB program flash memory with ECC
– 64 KB FlexNVM for data flash memory with ECC
and EEPROM emulation
– Up to 256 KB SRAM with ECC
– Up to 4 KB of FlexRAM for use as SRAM or
EEPROM emulation
– Up to 4 KB Code cache to minimize performance
impact of memory access latencies
– QuadSPI with HyperBus™ support
S32K1XX
• Mixed-signal analog
– Up to two 12-bit Analog-to-Digital Converter
(ADC) with up to 32 channel analog inputs per
module
– One Analog Comparator (CMP) with internal 8-bit
Digital to Analog Converter (DAC)
• Debug functionality
– Serial Wire JTAG Debug Port (SWJ-DP) combines
– Debug Watchpoint and Trace (DWT)
– Instrumentation Trace Macrocell (ITM)
– Test Port Interface Unit (TPIU)
– Flash Patch and Breakpoint (FPB) Unit
• Human-machine interface (HMI)
– Up to 156 GPIO pins with interrupt functionality
– Non-Maskable Interrupt (NMI)
• Communications interfaces
– Up to three Low Power Universal Asynchronous
Receiver/Transmitter (LPUART) modules with
DMA support and low power availability
– Up to three Low Power Serial Peripheral Interface
(LPSPI) modules with DMA support and low power
availability
– Up to two Low Power Inter-Integrated Circuit
(LPI2C) modules with DMA support and low power
availability
– Up to three FlexCAN modules (with optional CAN-
FD support)
– FlexIO module for flexible and high performance
serial interfaces
• Reliability, safety and security
– HW Security Engine (CSEc)
– Internal watchdog (WDOG)
– External Watchdog monitor (EWM) module
– Error-Correcting Code (ECC) on flash and SRAM
memories
– Cyclic Redundancy Check (CRC) module
– 128-bit Unique Identification (ID) number
– System Memory Protection Unit (System MPU)
This document contains information on a product under development. NXP
reserves the right to change or discontinue this product without notice.
Preliminary
• Timing and control
– Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM)
– One 16-bit Low Power Timer (LPTMR) with flexible wake up control
– Two Programmable Delay Blocks (PDB) with flexible trigger system
– One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels
– 32-bit Real Time Counter (RTC)
• I/O and package
– 32-pin QFN, 48-pin LQFP, 64-pin LQFP, 100-pin LQFP, MAPBGA-100, 144-pin LQFP, 176-pin LQFP package
options
• 16 channel DMA with up to 63 request sources using DMAMUX
S32K1xx Data Sheet, Rev. 3, 03/2017
2
Preliminary
NXP Semiconductors
Table of Contents
1
2
3
Block diagram.................................................................................... 4
Feature comparison............................................................................ 5
Ordering parts.....................................................................................6
3.1 Determining valid orderable parts ............................................ 6
3.2 Ordering information ................................................................ 7
4
General............................................................................................... 8
4.1 Absolute maximum ratings........................................................8
4.2 Voltage and current operating requirements..............................9
4.3 Thermal operating characteristics..............................................9
4.4 Power and ground pins.............................................................. 10
4.5 LVR, LVD and POR operating requirements............................12
4.6 Power mode transition operating behaviors.............................. 13
4.7 Power consumption................................................................... 14
4.7.1
Modes configuration.................................................... 17
6.4.2
6.3.2
6.3.1.2
6.2.5
SPLL electrical specifications .....................................26
6.3 Memory and memory interfaces................................................27
6.3.1
Flash memory module (FTFC) electrical
specifications................................................................27
6.3.1.1
Flash timing specifications —
commands................................................ 27
Reliability specifications..........................29
QuadSPI AC specifications..........................................29
6.4 Analog modules......................................................................... 34
6.4.1
ADC electrical specifications...................................... 34
6.4.1.1
6.4.1.2
12-bit ADC operating conditions............. 34
12-bit ADC electrical characteristics....... 36
CMP with 8-bit DAC electrical specifications............ 37
6.5 Communication modules........................................................... 41
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
LPUART electrical specifications............................... 41
LPSPI electrical specifications.................................... 41
LPI2C electrical specifications.................................... 48
FlexCAN electical specifications.................................49
SAI electrical specifications........................................ 49
Ethernet AC specifications.......................................... 51
Clockout frequency......................................................54
4.8 ESD handling ratings.................................................................17
4.9 EMC radiated emissions operating behaviors........................... 17
5
I/O parameters....................................................................................17
5.1 AC electrical characteristics...................................................... 17
5.2 General AC specifications......................................................... 18
5.3 DC electrical specifications at 3.3 V Range.............................. 18
5.4 DC electrical specifications at 5.0 V Range.............................. 19
5.5 AC electrical specifications at 3.3 V range .............................. 20
5.6 AC electrical specifications at 5 V range ................................. 21
5.7 Standard input pin capacitance.................................................. 21
5.8 Device clock specifications....................................................... 21
6
Peripheral operating requirements and behaviors.............................. 22
6.1 System modules......................................................................... 22
6.2 Clock interface modules............................................................ 22
6.2.1
6.2.2
6.2.3
External System Oscillator electrical specifications....22
External System Oscillator frequency specifications . 25
System Clock Generation (SCG) specifications.......... 25
6.2.3.1
Fast internal RC Oscillator (FIRC)
electrical specifications............................ 25
6.2.3.2
Slow internal RC oscillator (SIRC)
electrical specifications ........................... 26
6.2.4
Low Power Oscillator (LPO) electrical specifications
......................................................................................26
9
8
7
6.6 Debug modules.......................................................................... 54
6.6.1
6.6.2
6.6.3
SWD electrical specofications .................................... 54
Trace electrical specifications......................................56
JTAG electrical specifications..................................... 57
Thermal attributes.............................................................................. 60
7.1 Description.................................................................................60
7.2 Thermal characteristics..............................................................60
7.3 General notes for specifications at maximum junction
temperature................................................................................ 64
Dimensions.........................................................................................65
8.1 Obtaining package dimensions ................................................. 65
Pinouts................................................................................................66
9.1 Package pinouts and signal descriptions....................................66
10 Revision History.................................................................................66
S32K1xx Data Sheet, Rev. 3, 03/2017
NXP Semiconductors
Preliminary
3
Block diagram
1 Block diagram
The figure below shows a superset high level architecture block diagram of the device.
Other devices within the family have a subset of the features. See
Feature comparison
for
chip specific values.
ARM Cortex M0+ / M4F
Core
PPB
Async
Trace
port
JTAG &
Serial Wire
MCM
TPIU
SWJ-DP
NVIC
ITM
FPU
DSP
DCODE
ICODE
AWIC
AHB-AP
FPB
DWT
System
Clock generation
DMA
MUX
LPO
128 kHz
SIRC
8 MHz
FIRC
48 MHz
SOSC
4-40 MHz 8-40 MHz
Mux
System MPU
1
LMEM
Main SRAM
2
Upper region
Lower region
eDMA
TCD
512B
SPLL
EIM
LMEM
controller
Code Cache
ENET
S1
M0
S2
M1
M2
M3
S3
S0
Crossbar switch (AXBS-Lite)
System MPU
1
Mux
GPIO
System MPU
1
QuadSPI
System MPU
1
Flash memory
controller
FlexRAM/
SRAM
Peripheral bus controller
ERM
WDOG
12-bit ADC
LPI2C
FlexIO
Low Power
Timer
QSPI
LPIT
Code flash
memory
CSEc
Data flash
memory
EWM
CRC
CMP
8-bit DAC
LPUART
FlexCAN
FlexTimer
TRGMUX
LPSPI
PDB
RTC
LPIT
SAI
1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from
accessing restricted memory regions. This system MPU provides memory protection at the
level of the Crossbar Switch. Each Crossbar master (Core, DMA, Ethernet) can be assigned
different access rights to each protected memory region. The ARM M4 core version in this family
does not integrate the ARM Core MPU, which would concurrently monitor only core-initiated memory
accesses. In this document, the term MPU refers to NXP’s system MPU.
2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces"
chapter of the S32K14x Series Reference Manual.
Device architectural IP
on all S32K devices
Key:
Peripherals present
on all S32K devices
Peripherals present
on selected S32K devices
(see the "Feature Comparison"
section in the RM)
Figure 1. High-level architecture diagram for the S32K1xx family
S32K1xx Data Sheet, Rev. 3, 03/2017
4
Preliminary
NXP Semiconductors
Feature comparison
2 Feature comparison
The following figure summarizes the memory and package options for the S32K product
series and demonstrates where this device fits within the overall series. All devices which
share a common package are pin-to-pin compatible.
S32K11x
Parameter
Core
Frequency
IEEE-754 FPU
HW security module (CSEc)
CRC module
ISO 26262
Peripheral speed
System
S32K14x
K118
K142
K144
K146
ARM
®
Cortex
™
-M4F
up to 112 MHz
K148
K116
48 MHz
ARM
®
Cortex
™
-M0+
1x
capable up to ASIL-B
up to 48 MHz
1x
capable up to ASIL-B
up to 112 MHz
Crossbar
DMA
EWM
Memory protection unit
Watchdog
Low power modes
Number of I/Os
Single supply voltage
Operating temperature (Ta) Temperature ambient
Flash
Error correction code (ECC)
System RAM (including FlexRAM)
16 KB
2 KB
24 KB
32 KB
64 KB
4 KB
4 KB
2 KB (up to 32 KB D-Flash)
4 KB (up to 64 KB D-Flash)
4 KB (up to 512 KB D-Flash
as a part of 2 MB Flash)
1x
up to 42
2.7 - 5.5 V
-40 to +85ºC / +105ºC / +125ºC
128 KB
256 KB
256 KB
512 KB
up to 58
up to 89
1x
up to 128
2.7 - 5.5 V
-40 to +85ºC / +105ºC / +125ºC
1 MB
128 KB
2 MB
256 KB
up to 156
Memory
FlexRAM (also available as system RAM)
Cache
EEPROM emulated by FlexRAM
External memory interface
Low power interrupt timer
QuadSPI incl.
HyperBus™
1x
2x (16)
1x
1x
1x
1x (16)
1x (16)
1x
1x (64)
2x (16)
1x
1x
2x
1x
1x
1x
1x
(1x with FD)
1x
SWD, JTAG
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, COSMIC, Lauterbach, iSystems
QFN-32
LQFP-48
LQFP-48
LQFP-64
LQFP-64
LQFP-100
2x
(1x with FD)
2x
2x
2x
1x
3x
(1x with FD)
1x
SWD, JTAG (ITM, SWV, SWO)
NXP S32 Design Studio (GCC) + SDK,
IAR, GHS, COSMIC, Lauterbach, iSystems
LQFP-64
LQFP-100
MAPBGA-100
MAPBGA-100
LQFP-100
LQFP-144
MAPBGA-100
LQFP-144
LQFP-176
SWD, JTAG
(ITM, SWV,
SWO),ETM
3x
(2x with FD)
3x
3x
2x
3x
(3x with FD)
4x (32)
1x
1x
2x
1x (73)
2x (24)
1x (81)
2x (32)
1x
6x (48)
8x (64)
Timer
Analog
Communication
IDEs
Other
FlexTimer (16-bit counter) 8 channels
Low power timer (LPTMR)
Real time counter (RTC)
Programmable delay block (PDB)
Trigger mux (TRGMUX)
12-bit SAR ADC (1 MSPS each)
Comparator with 8-bit DAC
100 Mbit IEEE-1588 ethernet MAC
Serial audio interface (AC97, TDM, I2S)
(Supports LIN protocol versions 1.3, 2.0, 2.1, and SAE J2602)
Low power UART/LIN
Low power SPI
Low power I2C
FlexCAN
(CAN-FD ISO/CD 11898-1)
FlexIO (8 pins configurable as UART, SPI, I2C, I2S)
Debug & trace
Ecosystem
(IDE, compiler, debugger)
Packages
LEGEND:
Not implemented.
Available on the device.
Figure 2. S32K1xx product series comparison
S32K1xx Data Sheet, Rev. 3, 03/2017
NXP Semiconductors
Preliminary
5
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
