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CY62158H-45ZSXI

Description
SRAM - 异步 存储器 IC 8Mb(1M x 8) 并联 44-TSOP II
Categorysemiconductor    memory   
File Size390KB,16 Pages
ManufacturerCypress Semiconductor
Environmental Compliance
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CY62158H-45ZSXI Overview

SRAM - 异步 存储器 IC 8Mb(1M x 8) 并联 44-TSOP II

CY62158H-45ZSXI Parametric

Parameter NameAttribute value
category
MakerCypress Semiconductor
seriesMoBL®
Packagetray
memory typeVolatile
memory formatSRAM
technologySRAM - Asynchronous
storage8Mb(1M x 8)
memory interfacein parallel
Write cycle time - words, pages45ns
Voltage - Power supply4.5V ~ 5.5V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount type
Package/casing44-TSOP (0.400", 10.16mm wide)
Supplier device packaging44-TSOP II
interview time45 ns
Basic product numberCY62158
CY62158H MoBL
®
8-Mbit (1M words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
8-Mbit (1M words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Features
Functional Description
CY62158H is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC.
Device is accessed by asserting both chip enable inputs – CE
1
as LOW and CE
2
as HIGH.
Write to the device is performed by taking Chip Enable 1 (CE
1
)
LOW and Chip Enable 2 (CE
2
) HIGH and the Write Enable (WE)
input LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then
written into the location specified on the address pins (A
0
through
A
19
).
Read from the device is performed by taking Chip Enable 1 (CE
1
)
and Output Enable (OE) LOW and Chip Enable 2 (CE
2
) HIGH
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins will appear on the I/O pins.
The eight input and output pins (I/O
0
through I/O
7
) are placed in
a high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE
1
LOW and CE
2
HIGH and WE
LOW). See the
Truth Table – CY62158H on page 11
for a
complete description of read and write modes.
Ultra-low standby power
Typical standby current: 5.5
A
Maximum standby current: 16
A
High speed: 45 ns
Embedded error-correcting code (ECC) for single-bit error
correction
[1, 2]
Operating voltage range: 4.5 V to 5.5 V
1.0-V data retention
Transistor-transistor logic (TTL) compatible inputs and outputs
Available in Pb-free 44-pin TSOP II package
Logic Block Diagram – CY62158H
ECC ENCODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
DATA
IN
DRIVERS
ECC DECODER
SENSE 
AMPLIFIERS
1M x 8
RAM ARRAY
I/O
0
‐I/O
7
COLUMN 
DECODER
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
WE
OE
CE
2
CE
1
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer
AN88889
for details.
Cypress Semiconductor Corporation
Document Number: 001-96968 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 4, 2018
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