MT48LC8M8A2P-7E L:G datasheet, PDF

Datasheet> All Categories > semiconductor> memory> MT48LC8M8A2P-7E L:G

MT48LC8M8A2P-7E L:G: DescriptionSDRAM 存储器 IC 64Mb（8M x 8）并联 133 MHz 5.4 ns 54-TSOP II; Categorysemiconductor memory; File Size4MB，85 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric View All

MT48LC8M8A2P-7E L:G Overview

SDRAM 存储器 IC 64Mb（8M x 8）并联 133 MHz 5.4 ns 54-TSOP II

MT48LC8M8A2P-7E L:G Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	box
memory type	Volatile
memory format	DRAM
technology	SDRAM
storage	64Mb（8M x 8）
memory interface	in parallel
Write cycle time - words, pages	14ns
Voltage - Power supply	3V ~ 3.6V
Operating temperature	0°C ~ 70°C（TA）
Installation type	surface mount type
Package/casing	54-TSOP (0.400", 10.16mm wide)
Supplier device packaging	54-TSOP II
Clock frequency	133 MHz
interview time	5.4 ns
Basic product number	MT48LC8M8A2

Preview

Download Datasheet

View All

128Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 Banks

MT48LC16M8A2 – 4 Meg x 8 x 4 Banks

MT48LC8M16A2 – 2 Meg x 16 x 4 Banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths (BL): 1, 2, 4, 8, or full

page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh modes: Standard and low power

(not available on AT devices)

• Auto Refresh

– 64ms, 4096-cycle refresh (commercial and

industrial)

– 16ms, 4096-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Plastic package – OCPL

– 54-pin TSOP II (400 mil)

– 54-pin TSOP II (400 mil) Pb-free

– 60-ball TFBGA (8mm x 16mm)

– 60-ball TFBGA (8mm x 16mm) Pb-

free

– 54-ball VFBGA (x16 only) (8mm x

8mm)

– 54-ball VFBGA (x16 only) (8mm x

8mm) Pb-free

• Timing – cycle time

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

– 6.0ns @ CL = 3 (x16 only)

• Self refresh

– Standard

– Low power

• Revision

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

Notes:

1. Contact Micron for availability.

2. Off-center parting line.

3. Only available on Revision G.

Options

Marking

-75

-7E

-6A

None

:G/:L

None

Options

• Configurations

– 32 Meg x 4 (8 Meg x 4 x 4 banks)

– 16 Meg x 8 (4 Meg x 8 x 4 banks)

– 8 Meg x 16 (2 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = 2 CLK

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-6A

-75

-7E

Clock

Frequency (MHz)

167

133

Marking

32M4

16M8

8M16

Target

RCD-

RP-CL

3-3-3

2-2-2

RCD

(ns)

CL (ns)

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ..................................................................................................... 11

Package Dimensions ....................................................................................................................................... 15

Temperature and Thermal Impedance ............................................................................................................ 18

Electrical Specifications .................................................................................................................................. 22

Electrical Specifications – I

Parameters ........................................................................................................ 24

Electrical Specifications – AC Operating Conditions ......................................................................................... 26

Functional Description ................................................................................................................................... 29

Commands .................................................................................................................................................... 30

COMMAND INHIBIT .................................................................................................................................. 30

NO OPERATION (NOP) ............................................................................................................................... 31

LOAD MODE REGISTER (LMR) ................................................................................................................... 31

ACTIVE ...................................................................................................................................................... 31

READ ......................................................................................................................................................... 32

WRITE ....................................................................................................................................................... 33

PRECHARGE .............................................................................................................................................. 34

BURST TERMINATE ................................................................................................................................... 34

REFRESH ................................................................................................................................................... 35

AUTO REFRESH ..................................................................................................................................... 35

SELF REFRESH ....................................................................................................................................... 35

Truth Tables ................................................................................................................................................... 36

Initialization .................................................................................................................................................. 41

Mode Register ................................................................................................................................................ 43

Burst Length .............................................................................................................................................. 45

Burst Type .................................................................................................................................................. 45

CAS Latency ............................................................................................................................................... 47

Operating Mode ......................................................................................................................................... 47

Write Burst Mode ....................................................................................................................................... 47

Bank/Row Activation ...................................................................................................................................... 48

READ Operation ............................................................................................................................................. 49

WRITE Operation ........................................................................................................................................... 58

Burst Read/Single Write .............................................................................................................................. 65

PRECHARGE Operation .................................................................................................................................. 66

Auto Precharge ........................................................................................................................................... 66

AUTO REFRESH Operation ............................................................................................................................. 78

SELF REFRESH Operation ............................................................................................................................... 80

Power-Down .................................................................................................................................................. 82

Clock Suspend ............................................................................................................................................... 83

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 32 Meg x 4 Functional Block Diagram ................................................................................................. 8

Figure 2: 16 Meg x 8 Functional Block Diagram ................................................................................................. 9

Figure 3: 8 Meg x 16 Functional Block Diagram ............................................................................................... 10

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11

Figure 5: 60-Ball FBGA (TopView) .................................................................................................................. 12

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13

Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 15

Figure 8: 60-Ball TFBGA (x8 Device), 8mm x 16mm – Package Code FB/BB ...................................................... 16

Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4 ....................................................... 17

Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 20

Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21

Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 21

Figure 13: ACTIVE Command ........................................................................................................................ 31

Figure 14: READ Command ........................................................................................................................... 32

Figure 15: WRITE Command ......................................................................................................................... 33

Figure 16: PRECHARGE Command ................................................................................................................ 34

Figure 17: Initialize and Load Mode Register .................................................................................................. 42

Figure 18: Mode Register Definition ............................................................................................................... 44

Figure 19: CAS Latency .................................................................................................................................. 47

Figure 20: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 48

Figure 21: Consecutive READ Bursts .............................................................................................................. 50

Figure 22: Random READ Accesses ................................................................................................................ 51

Figure 23: READ-to-WRITE ............................................................................................................................ 52

Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 53

Figure 25: READ-to-PRECHARGE .................................................................................................................. 53

Figure 26: Terminating a READ Burst ............................................................................................................. 54

Figure 27: Alternating Bank Read Accesses ..................................................................................................... 55

Figure 28: READ Continuous Page Burst ......................................................................................................... 56

Figure 29: READ – DQM Operation ................................................................................................................ 57

Figure 30: WRITE Burst ................................................................................................................................. 58

Figure 31: WRITE-to-WRITE .......................................................................................................................... 59

Figure 32: Random WRITE Cycles .................................................................................................................. 60

Figure 33: WRITE-to-READ ............................................................................................................................ 60

Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 61

Figure 35: Terminating a WRITE Burst ............................................................................................................ 62

Figure 36: Alternating Bank Write Accesses ..................................................................................................... 63

Figure 37: WRITE – Continuous Page Burst ..................................................................................................... 64

Figure 38: WRITE – DQM Operation ............................................................................................................... 65

Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 67

Figure 40: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 68

Figure 41: READ With Auto Precharge ............................................................................................................ 69

Figure 42: READ Without Auto Precharge ....................................................................................................... 70

Figure 43: Single READ With Auto Precharge .................................................................................................. 71

Figure 44: Single READ Without Auto Precharge ............................................................................................. 72

Figure 45: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 73

Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 73

Figure 47: WRITE With Auto Precharge ........................................................................................................... 74

Figure 48: WRITE Without Auto Precharge ..................................................................................................... 75

Figure 49: Single WRITE With Auto Precharge ................................................................................................. 76

Figure 50: Single WRITE Without Auto Precharge ............................................................................................ 77

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

New Current Drive Amplifier 01

4-digit incandescent lamp display circuit

Retriggerable monostable circuit diagram

Enhanced European SMS Phone Chip (Protocol 1/2) Circuit

Blocking infrared control circuit

Sound control switch and amplifier schematic diagram

Which tool do you usually use to debug network programs when doing network design?: I am going to use 44b0 to learn how to program network communication software. There seems to be a tool that is specifically used to detect computer network data, just like Bus Hound looks at USB data...; kakalin Embedded System

Is plasma reaching its end?: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 20:00[/i] Plasma (PDP) refers to a TV product that produces color effects by filling a mixed gas between two thin glass plates, applying v...; leslie Mobile and portable

How to turn off the PWM module of PIC microcontroller after it is turned on?: 1. Is it by changing the TRISX register of the CCP pin? 2. Or changing CCXM "3:0" to turn off PWM? 3. I can achieve the first method of customizing the timer through PROTES simulation, but the second ...; 男哥 Microchip MCU

Two questions: 1. The Ndis library does not send irp to the interface function (such as initialization function, etc.) of the nids miniport driver. Where does the irp in the code come from? Is the ndis miniport driv...; almax12 Embedded System

Take MCU's high-quality courses and turn yourself into an exam expert in no time!: [color=#ff0000][b]Activity time:[/b][/color][color=#3e3a39] March 16, 2015 - April 19, 2015[/color] [color=#ff0000][b]Activity process:[/b][/color] [list] [*][color=#2f2d2d][url=https://home.eeworld.c...; EEWORLD社区 Microcontroller MCU

Everyone is using STM32. Have you seen others make Nucleo + Scratch? Suitable for children's graphic programming: Everyone is using STM32. Have you seen others make Nucleo + Scratch? Suitable for children's graphic programming...; 蓝雨夜 stm32/stm8

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components