MT48LC4M16A2P-7E IT:G datasheet, PDF

Datasheet> All Categories > semiconductor> memory> MT48LC4M16A2P-7E IT:G

MT48LC4M16A2P-7E IT:G: DescriptionSDRAM 存储器 IC 64Mb（4M x 16）并联 133 MHz 5.4 ns 54-TSOP II; Categorysemiconductor memory; File Size4MB，85 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric View All

MT48LC4M16A2P-7E IT:G Overview

SDRAM 存储器 IC 64Mb（4M x 16）并联 133 MHz 5.4 ns 54-TSOP II

MT48LC4M16A2P-7E IT:G Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	tray
memory type	Volatile
memory format	DRAM
technology	SDRAM
storage	64Mb（4M x 16）
memory interface	in parallel
Write cycle time - words, pages	14ns
Voltage - Power supply	3V ~ 3.6V
Operating temperature	-40°C ~ 85°C（TA）
Installation type	surface mount type
Package/casing	54-TSOP (0.400", 10.16mm wide)
Supplier device packaging	54-TSOP II
Clock frequency	133 MHz
interview time	5.4 ns
Basic product number	MT48LC4M16A2

Preview

Download Datasheet

View All

128Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM

MT48LC32M4A2 – 8 Meg x 4 x 4 Banks

MT48LC16M8A2 – 4 Meg x 8 x 4 Banks

MT48LC8M16A2 – 2 Meg x 16 x 4 Banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths (BL): 1, 2, 4, 8, or full

page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh modes: Standard and low power

(not available on AT devices)

• Auto Refresh

– 64ms, 4096-cycle refresh (commercial and

industrial)

– 16ms, 4096-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Plastic package – OCPL

– 54-pin TSOP II (400 mil)

– 54-pin TSOP II (400 mil) Pb-free

– 60-ball TFBGA (8mm x 16mm)

– 60-ball TFBGA (8mm x 16mm) Pb-

free

– 54-ball VFBGA (x16 only) (8mm x

8mm)

– 54-ball VFBGA (x16 only) (8mm x

8mm) Pb-free

• Timing – cycle time

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

– 6.0ns @ CL = 3 (x16 only)

• Self refresh

– Standard

– Low power

• Revision

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

Notes:

1. Contact Micron for availability.

2. Off-center parting line.

3. Only available on Revision G.

Options

Marking

-75

-7E

-6A

None

:G/:L

None

Options

• Configurations

– 32 Meg x 4 (8 Meg x 4 x 4 banks)

– 16 Meg x 8 (4 Meg x 8 x 4 banks)

– 8 Meg x 16 (2 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = 2 CLK

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-6A

-75

-7E

Clock

Frequency (MHz)

167

133

Marking

32M4

16M8

8M16

Target

RCD-

RP-CL

3-3-3

2-2-2

RCD

(ns)

CL (ns)

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ..................................................................................................... 11

Package Dimensions ....................................................................................................................................... 15

Temperature and Thermal Impedance ............................................................................................................ 18

Electrical Specifications .................................................................................................................................. 22

Electrical Specifications – I

Parameters ........................................................................................................ 24

Electrical Specifications – AC Operating Conditions ......................................................................................... 26

Functional Description ................................................................................................................................... 29

Commands .................................................................................................................................................... 30

COMMAND INHIBIT .................................................................................................................................. 30

NO OPERATION (NOP) ............................................................................................................................... 31

LOAD MODE REGISTER (LMR) ................................................................................................................... 31

ACTIVE ...................................................................................................................................................... 31

READ ......................................................................................................................................................... 32

WRITE ....................................................................................................................................................... 33

PRECHARGE .............................................................................................................................................. 34

BURST TERMINATE ................................................................................................................................... 34

REFRESH ................................................................................................................................................... 35

AUTO REFRESH ..................................................................................................................................... 35

SELF REFRESH ....................................................................................................................................... 35

Truth Tables ................................................................................................................................................... 36

Initialization .................................................................................................................................................. 41

Mode Register ................................................................................................................................................ 43

Burst Length .............................................................................................................................................. 45

Burst Type .................................................................................................................................................. 45

CAS Latency ............................................................................................................................................... 47

Operating Mode ......................................................................................................................................... 47

Write Burst Mode ....................................................................................................................................... 47

Bank/Row Activation ...................................................................................................................................... 48

READ Operation ............................................................................................................................................. 49

WRITE Operation ........................................................................................................................................... 58

Burst Read/Single Write .............................................................................................................................. 65

PRECHARGE Operation .................................................................................................................................. 66

Auto Precharge ........................................................................................................................................... 66

AUTO REFRESH Operation ............................................................................................................................. 78

SELF REFRESH Operation ............................................................................................................................... 80

Power-Down .................................................................................................................................................. 82

Clock Suspend ............................................................................................................................................... 83

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

128Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 32 Meg x 4 Functional Block Diagram ................................................................................................. 8

Figure 2: 16 Meg x 8 Functional Block Diagram ................................................................................................. 9

Figure 3: 8 Meg x 16 Functional Block Diagram ............................................................................................... 10

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11

Figure 5: 60-Ball FBGA (TopView) .................................................................................................................. 12

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13

Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 15

Figure 8: 60-Ball TFBGA (x8 Device), 8mm x 16mm – Package Code FB/BB ...................................................... 16

Figure 9: 54-Ball VFBGA (x16 Device), 8mm x 8mm – Package Code F4/B4 ....................................................... 17

Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 20

Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21

Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 21

Figure 13: ACTIVE Command ........................................................................................................................ 31

Figure 14: READ Command ........................................................................................................................... 32

Figure 15: WRITE Command ......................................................................................................................... 33

Figure 16: PRECHARGE Command ................................................................................................................ 34

Figure 17: Initialize and Load Mode Register .................................................................................................. 42

Figure 18: Mode Register Definition ............................................................................................................... 44

Figure 19: CAS Latency .................................................................................................................................. 47

Figure 20: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 48

Figure 21: Consecutive READ Bursts .............................................................................................................. 50

Figure 22: Random READ Accesses ................................................................................................................ 51

Figure 23: READ-to-WRITE ............................................................................................................................ 52

Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 53

Figure 25: READ-to-PRECHARGE .................................................................................................................. 53

Figure 26: Terminating a READ Burst ............................................................................................................. 54

Figure 27: Alternating Bank Read Accesses ..................................................................................................... 55

Figure 28: READ Continuous Page Burst ......................................................................................................... 56

Figure 29: READ – DQM Operation ................................................................................................................ 57

Figure 30: WRITE Burst ................................................................................................................................. 58

Figure 31: WRITE-to-WRITE .......................................................................................................................... 59

Figure 32: Random WRITE Cycles .................................................................................................................. 60

Figure 33: WRITE-to-READ ............................................................................................................................ 60

Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 61

Figure 35: Terminating a WRITE Burst ............................................................................................................ 62

Figure 36: Alternating Bank Write Accesses ..................................................................................................... 63

Figure 37: WRITE – Continuous Page Burst ..................................................................................................... 64

Figure 38: WRITE – DQM Operation ............................................................................................................... 65

Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 67

Figure 40: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 68

Figure 41: READ With Auto Precharge ............................................................................................................ 69

Figure 42: READ Without Auto Precharge ....................................................................................................... 70

Figure 43: Single READ With Auto Precharge .................................................................................................. 71

Figure 44: Single READ Without Auto Precharge ............................................................................................. 72

Figure 45: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 73

Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 73

Figure 47: WRITE With Auto Precharge ........................................................................................................... 74

Figure 48: WRITE Without Auto Precharge ..................................................................................................... 75

Figure 49: Single WRITE With Auto Precharge ................................................................................................. 76

Figure 50: Single WRITE Without Auto Precharge ............................................................................................ 77

PDF: 09005aef8091e66d

128mb_x4x8x16_sdram.pdf - Rev. V 09/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

LM567 decoding alarm circuit diagram

Time controller circuit that turns on or off the power supply regularly

Sensitive Geiger counter circuit diagram

Steering control of single-phase motor converted from three-phase motor＿2

Monolithic radio circuit

Digitally controlled adjustable integrated regulated power supply

Newbie, help!: I am currently working on something related to a hydrogen generator and have come across a problem. A flow display is installed on the panel. The flow is calculated based on the electrolysis current, ...; chemical Analog electronics

Development direction and strategic trend of communications industry: Looking at the future development of the communications industry itself, we need to look at the development of the industry in the context of great integration. The first is the big industry under the...; liudong2008lldd RF/Wirelessly

PIC16F1459: The compilation environment is MPLAB IDE V8.9, the compiler is HI TECH PICC V9.83, and the selected chip is PIC16F1459, but the compiler only provides assembly language, not C language. Why?...; xzfx Microchip MCU

[NXP Rapid IoT Review] + Mobile Synchronizer 6: [i=s] This post was last edited by Beifang on 2019-1-21 10:06 [/i] 1. The use of third-party cloud provides a rich development environment in the entire development environment. In the front-end devel...; 北方 RF/Wirelessly

[Design plan] STM32F429i development board LCD touch display play notes: The STM32F429I-DISCO development board comes with an LCD display and a touch panel, making the board more playable. The program under Touch_Panel in the official example package STM32F429I-Discovery_F...; sacq stm32/stm8

Look at this familiar thing and explain it: Everyone is familiar with this! nrf2401; Let's take a look at thisWhy is the power P negative? What does it mean? Does it mean that the transmission distance is very short when it is -20?...; zhengzhoutie RF/Wirelessly

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components