MT46H32M16LFBF-6 AT:C datasheet, PDF

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MT46H32M16LFBF-6 AT:C: DescriptionSDRAM - 移动 LPDDR 存储器 IC 512Mb（32M x 16）并联 166 MHz 5 ns 60-VFBGA（8x9）; Categorysemiconductor memory; File Size1MB，96 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46H32M16LFBF-6 AT:C Overview

SDRAM - 移动 LPDDR 存储器 IC 512Mb（32M x 16）并联 166 MHz 5 ns 60-VFBGA（8x9）

MT46H32M16LFBF-6 AT:C Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	Pipe fittings
memory type	Volatile
memory format	DRAM
technology	SDRAM - Mobile LPDDR
storage	512Mb（32M x 16）
memory interface	in parallel
Write cycle time - words, pages	15ns
Voltage - Power supply	1.7V ~ 1.95V
Operating temperature	-40°C ~ 105°C（TA）
Installation type	surface mount type
Package/casing	60-VFBGA
Supplier device packaging	60-VFBGA（8x9）
Clock frequency	166 MHz
interview time	5 ns
Basic product number	MT46H32M16

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512Mb: x16, x32 Automotive LPDDR SDRAM

Features

Automotive LPDDR SDRAM

MT46H32M16LF – 8 Meg x 16 x 4 banks

MT46H16M32LF – 4 Meg x 32 x 4 banks

MT46H16M32LG – 4 Meg x 32 x 4 banks

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh, 32ms for automotive temperature

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-6

Clock Rate

200 MHz

166 MHz

Access Time

5.0ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

– 16 Meg x 32 (4 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard addressing

• Plastic "green" package

– 60-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• Timing – cycle time

– 5ns @ CL = 3 (200 MHz)

– 6ns @ CL = 3 (166 MHz)

• Power

– Standard I

DD2

DD6

– Low-power I

DD2

DD6

• Product certification

– Automotive

• Operating temperature range

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Design revision

Notes:

Marking

32M16

16M32

-5

-6

None

1. Only available for x16 configuration.

2. Only available for x32 configuration.

PDF: 09005aef846e285e

t67m_embedded_lpddr_512mb.pdf - Rev. D 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb: x16, x32 Automotive LPDDR SDRAM

Features

Contents

General Description ......................................................................................................................................... 8

Functional Block Diagrams ............................................................................................................................... 9

Ball Assignments ............................................................................................................................................ 11

Ball Descriptions ............................................................................................................................................ 13

Package Dimensions ....................................................................................................................................... 15

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – I

Parameters ........................................................................................................ 21

Electrical Specifications – AC Operating Conditions ......................................................................................... 27

Output Drive Characteristics ........................................................................................................................... 31

Functional Description ................................................................................................................................... 34

Commands .................................................................................................................................................... 35

DESELECT ................................................................................................................................................. 36

NO OPERATION ......................................................................................................................................... 36

LOAD MODE REGISTER ............................................................................................................................. 36

ACTIVE ...................................................................................................................................................... 36

READ ......................................................................................................................................................... 37

WRITE ....................................................................................................................................................... 38

PRECHARGE .............................................................................................................................................. 39

BURST TERMINATE ................................................................................................................................... 40

AUTO REFRESH ......................................................................................................................................... 40

SELF REFRESH ........................................................................................................................................... 41

DEEP POWER-DOWN ................................................................................................................................. 41

Truth Tables ................................................................................................................................................... 42

State Diagram ................................................................................................................................................ 47

Initialization .................................................................................................................................................. 48

Standard Mode Register .................................................................................................................................. 51

Burst Length .............................................................................................................................................. 52

Burst Type .................................................................................................................................................. 52

CAS Latency ............................................................................................................................................... 53

Operating Mode ......................................................................................................................................... 54

Extended Mode Register ................................................................................................................................. 55

Temperature-Compensated Self Refresh ...................................................................................................... 55

Partial-Array Self Refresh ............................................................................................................................ 56

Output Drive Strength ................................................................................................................................ 56

Status Read Register ....................................................................................................................................... 57

Bank/Row Activation ...................................................................................................................................... 59

READ Operation ............................................................................................................................................. 60

WRITE Operation ........................................................................................................................................... 71

PRECHARGE Operation .................................................................................................................................. 83

Auto Precharge ............................................................................................................................................... 83

Concurrent Auto Precharge ......................................................................................................................... 84

AUTO REFRESH Operation ............................................................................................................................. 89

SELF REFRESH Operation ............................................................................................................................... 90

Power-Down .................................................................................................................................................. 91

Deep Power-Down ..................................................................................................................................... 93

Clock Change Frequency ................................................................................................................................ 95

Revision History ............................................................................................................................................. 96

Rev. D – 02/14 ............................................................................................................................................. 96

Rev. C – 11/13 ............................................................................................................................................. 96

Rev. B – 03/13 ............................................................................................................................................. 96

PDF: 09005aef846e285e

t67m_embedded_lpddr_512mb.pdf - Rev. D 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x16, x32 Automotive LPDDR SDRAM

Features

List of Figures

Figure 1: 512Mb Mobile LPDDR Part Numbering .............................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12

Figure 6: 60-Ball VFBGA (8mm x 9mm); Package Code: BF .............................................................................. 15

Figure 7: 90-Ball VFBGA (8mm x 13mm); Package Codes: B5 (SAC105), BQ (SAC305) ........................................ 16

Figure 8: SSTL Clock Input ............................................................................................................................. 19

Figure 9: Differential Clock Amplitude ........................................................................................................... 19

Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 26

Figure 11: ACTIVE Command ........................................................................................................................ 37

Figure 12: READ Command ........................................................................................................................... 38

Figure 13: WRITE Command ......................................................................................................................... 39

Figure 14: PRECHARGE Command ................................................................................................................ 40

Figure 15: DEEP POWER-DOWN Command ................................................................................................... 41

Figure 16: Simplified State Diagram ............................................................................................................... 47

Figure 17: Initialize and Load Mode Registers ................................................................................................. 49

Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 50

Figure 19: Standard Mode Register Definition ................................................................................................. 51

Figure 20: CAS Latency .................................................................................................................................. 54

Figure 21: Extended Mode Register ................................................................................................................ 55

Figure 22: Status Read Register Timing ........................................................................................................... 57

Figure 23: Status Register Definition .............................................................................................................. 58

Figure 24: READ Burst ................................................................................................................................... 61

Figure 25: Consecutive READ Bursts .............................................................................................................. 62

Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 63

Figure 27: Random Read Accesses .................................................................................................................. 64

Figure 28: Terminating a READ Burst ............................................................................................................. 65

Figure 29: READ-to-WRITE ............................................................................................................................ 66

Figure 30: READ-to-PRECHARGE .................................................................................................................. 67

Figure 31: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 68

Figure 32: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 69

Figure 33: Data Output Timing –

AC and

DQSCK .......................................................................................... 70

Figure 34: Data Input Timing ......................................................................................................................... 72

Figure 35: Write – DM Operation .................................................................................................................... 73

Figure 36: WRITE Burst ................................................................................................................................. 74

Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 75

Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75

Figure 39: Random WRITE Cycles .................................................................................................................. 76

Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 77

Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 78

Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 79

Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 80

Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81

Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 82

Figure 46: Bank Read – With Auto Precharge ................................................................................................... 85

Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 86

Figure 48: Bank Write – With Auto Precharge .................................................................................................. 87

Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 88

Figure 50: Auto Refresh Mode ........................................................................................................................ 89

PDF: 09005aef846e285e

t67m_embedded_lpddr_512mb.pdf - Rev. D 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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