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MT41J64M16JT-15E AAT:G

Description
SDRAM - DDR3 存储器 IC 1Gb(64M x 16) 并联 667 MHz 96-FBGA(8x14)
Categorysemiconductor    memory   
File Size8MB,181 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
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MT41J64M16JT-15E AAT:G Overview

SDRAM - DDR3 存储器 IC 1Gb(64M x 16) 并联 667 MHz 96-FBGA(8x14)

MT41J64M16JT-15E AAT:G Parametric

Parameter NameAttribute value
category
MakerMicron Technology
seriesAutomotive, AEC-Q100
Packagetray
memory typeVolatile
memory formatDRAM
technologySDRAM - DDR3
storage1Gb(64M x 16)
memory interfacein parallel
Write cycle time - words, pages-
Voltage - Power supply1.425V ~ 1.575V
Operating temperature-40°C ~ 105°C(TC)
Installation typesurface mount type
Package/casing96-TFBGA
Supplier device packaging96-FBGA(8x14)
Clock frequency667 MHz
Basic product numberMT41J64M16
1Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J256M4 – 32 Meg x 4 x 8 Banks
MT41J128M8 – 16 Meg x 8 x 8 Banks
MT41J64M16 – 8 Meg x 16 x 8 Banks
Features
V
DD
= V
DD
Q = +1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11
POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2
CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on
t
CK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0
o
C to 95
o
C
64ms, 8,192 cycle refresh at 0
o
C to 85
o
C
32ms at 85
o
C to 95
o
C
Clock frequency range of 300–800 MHz
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Options
• Configuration
256 Meg x 4
128 Meg x 8
64 Meg x 16
• FBGA package (Pb-free) - x4, x8
78-ball FBGA (8mm x 11.5mm) Rev. F
78-ball FBGA (9mm x 11.5mm) Rev. D
86-ball FBGA (9mm x 15.5mm) Rev. B
• FBGA package (Pb-free) - x16
96-ball FBGA (9mm x 15.5mm) Rev. B
• Timing - cycle time
1.25ns @ CL = 11 (DDR3-1600)
1.25ns @ CL = 10 (DDR3-1600)
1.25ns @ CL = 9 (DDR3-1600)
1.5ns @ CL = 10 (DDR3-1333)
1.5ns @ CL = 9 (DDR3-1333)
1.5ns @ CL = 8 (DDR3-1333)
1.87ns @ CL = 8 (DDR3-1066)
1.87ns @ CL = 7 (DDR3-1066)
2.5ns @ CL = 6 (DDR3-800)
2.5ns @ CL = 5 (DDR3-800)
• Revision
Marking
256M4
128M8
64M16
JP
HX
BY
LA
-125
-125E
-125F
-15
-15E
-15F
-187
-187E
-25
-25E
:B/:D/:F
Table 1:
Key Timing Parameters
Data Rate (MT/s) Target
t
RCD-
t
RP-CL
1600
1600
1600
1333
1333
1333
1066
1066
800
800
11-11-11
10-10-10
9-9-9
10-10-10
9-9-9
8-8-8
8-8-8
7-7-7
6-6-6
5-5-5
t
RCD
Speed Grade
-125
-125E
-125F
-15
-15E
-15F
-187
-187E
-25
-25E
(ns)
t
RP
(ns)
CL (ns)
13.75
12.5
11.25
15
13.5
12
15
13.1
15
12.5
13.75
12.5
11.25
15
13.5
12
15
13.1
15
12.5
13.75
12.5
11.25
15
13.5
12
15
13.1
15
12.5
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D1 .fm - Rev. F 11/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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