MT42L32M32D2AC-25 AIT:A datasheet, PDF

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MT42L32M32D2AC-25 AIT:A: DescriptionSDRAM - 移动 LPDDR2 存储器 IC 1Gb（32M x 32）并联 400 MHz 134-VFBGA（10x11.5）; Categorysemiconductor memory; File Size2MB，150 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT42L32M32D2AC-25 AIT:A Overview

SDRAM - 移动 LPDDR2 存储器 IC 1Gb（32M x 32）并联 400 MHz 134-VFBGA（10x11.5）

MT42L32M32D2AC-25 AIT:A Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	Automotive, AEC-Q100
Package	tray
memory type	Volatile
memory format	DRAM
technology	SDRAM - Mobile LPDDR2
storage	1Gb（32M x 32）
memory interface	in parallel
Write cycle time - words, pages	-
Voltage - Power supply	1.14V ~ 1.95V
Operating temperature	-25°C ~ 85°C（TC）
Installation type	surface mount type
Package/casing	134-VFBGA
Supplier device packaging	134-VFBGA（10x11.5）
Clock frequency	400 MHz
Basic product number	MT42L32M32

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512Mb Automotive Mobile LPDDR2 SDRAM

Features

Automotive Mobile LPDDR2 SDRAM

MT42L32M16D1, MT42L32M32D2, MT42L16M32D1

Features

• Ultra low-voltage core and I/O power supplies

– V

DD2

= 1.14–1.30V

– V

DDCA

DDQ

= 1.14–1.30V

– V

DD1

= 1.70–1.95V

• Clock frequency range

– 400–10 MHz (data rate range: 800–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Four internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• On-chip temperature sensor to control self refresh

rate

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed Clock Rate Data Rate

Grade

(MHz)

(Mb/s/pin)

-25

-3

400

333

800

667

RCD/

Options

• V

DD2

: 1.2V

• Configuration

– 4 Meg x 32 x 4 banks

– 8 Meg x 16 x 4 banks

– 2 x 8 Meg x 16 x 4 banks

• Device type

– LPDDR2-S4, 1 die in package

– LPDDR2-S4, 2 die in package

• FBGA “green” package

– 121-ball FBGA (6.5mm x 8mm)

– 134-ball FBGA (10mm x 11.5mm)

– 168-ball FBGA (12mm x 12mm)

• Timing – cycle time

– 2.5ns @ RL = 6

– 3.0ns @ RL = 5

• Automotive certified

– Package-level burn-in

• Operating temperature range

– From –40°C to +85°C

– From –40°C to +105°C

• Revision

Marking

16M32

32M16

32M32

AB/FE

-25

-3

Typical

PDF: 09005aef84d56533

u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb Automotive Mobile LPDDR2 SDRAM

Features

Contents

General Description ......................................................................................................................................... 9

General Notes .............................................................................................................................................. 9

Specifications ........................................................................................................................................... 10

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 18

Ball Assignments and Descriptions ................................................................................................................. 21

Functional Description ................................................................................................................................... 25

Power-Up ....................................................................................................................................................... 26

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 28

Power-Off ....................................................................................................................................................... 28

Uncontrolled Power-Off .............................................................................................................................. 29

Mode Register Definition ................................................................................................................................ 29

Mode Register Assignments and Definitions ................................................................................................ 29

ACTIVATE Command ..................................................................................................................................... 40

8-Bank Device Operation ............................................................................................................................ 40

Read and Write Access Modes ......................................................................................................................... 41

Burst READ Command ................................................................................................................................... 41

READs Interrupted by a READ ..................................................................................................................... 48

Burst WRITE Command .................................................................................................................................. 48

WRITEs Interrupted by a WRITE ................................................................................................................. 51

BURST TERMINATE Command ...................................................................................................................... 51

Write Data Mask ............................................................................................................................................. 53

PRECHARGE Command ................................................................................................................................. 54

READ Burst Followed by PRECHARGE ......................................................................................................... 55

WRITE Burst Followed by PRECHARGE ....................................................................................................... 56

Auto Precharge ........................................................................................................................................... 57

READ Burst with Auto Precharge ................................................................................................................. 57

WRITE Burst with Auto Precharge ............................................................................................................... 58

REFRESH Command ...................................................................................................................................... 60

REFRESH Requirements ............................................................................................................................. 66

SELF REFRESH Operation ............................................................................................................................... 68

Partial-Array Self Refresh – Bank Masking .................................................................................................... 69

Partial-Array Self Refresh – Segment Masking .............................................................................................. 70

MODE REGISTER READ ................................................................................................................................. 71

Temperature Sensor ................................................................................................................................... 73

DQ Calibration ........................................................................................................................................... 75

MODE REGISTER WRITE Command ............................................................................................................... 77

MRW RESET Command .............................................................................................................................. 77

MRW ZQ Calibration Commands ................................................................................................................ 78

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 80

Power-Down .................................................................................................................................................. 80

Deep Power-Down ......................................................................................................................................... 87

Input Clock Frequency Changes and Stop Events ............................................................................................. 88

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 88

Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 89

NO OPERATION Command ............................................................................................................................ 89

Simplified Bus Interface State Diagram ........................................................................................................ 89

Truth Tables ................................................................................................................................................... 91

Electrical Specifications .................................................................................................................................. 99

Absolute Maximum Ratings ........................................................................................................................ 99

PDF: 09005aef84d56533

u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb Automotive Mobile LPDDR2 SDRAM

Features

Input/Output Capacitance .......................................................................................................................... 99

Electrical Specifications – I

Specifications and Conditions ........................................................................... 100

AC and DC Operating Conditions ................................................................................................................... 103

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 105

REF

Tolerances ......................................................................................................................................... 106

Input Signal .............................................................................................................................................. 106

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 109

Single-Ended Requirements for Differential Signals .................................................................................... 110

Differential Input Crosspoint Voltage ......................................................................................................... 112

Input Slew Rate ......................................................................................................................................... 112

Output Characteristics and Operating Conditions ........................................................................................... 113

Single-Ended Output Slew Rate .................................................................................................................. 114

Differential Output Slew Rate ..................................................................................................................... 115

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 118

Output Driver Impedance .............................................................................................................................. 118

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 119

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 120

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 120

Clock Specification ........................................................................................................................................ 124

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 125

Clock Period Jitter .......................................................................................................................................... 125

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 125

Cycle Time Derating for Core Timing Parameters ........................................................................................ 126

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 126

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 126

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 126

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 127

Refresh Requirements .................................................................................................................................... 128

AC Timing ..................................................................................................................................................... 129

CA and CS# Setup, Hold, and Derating ........................................................................................................... 135

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 142

Revision History ............................................................................................................................................ 149

Rev. J – 10/15 ............................................................................................................................................. 149

Rev. I – 07/15 ............................................................................................................................................. 149

Rev. H – 05/15 ............................................................................................................................................ 149

Rev. G – 11/14 ............................................................................................................................................ 149

Rev. F – 08/14 ............................................................................................................................................ 149

Rev. E – 06/14 ............................................................................................................................................ 149

Rev. D – 07/13 ............................................................................................................................................ 149

Rev. C – 04/13 ............................................................................................................................................ 149

Rev. B – 03/13 ............................................................................................................................................ 149

Rev. A – 08/12 ............................................................................................................................................ 150

PDF: 09005aef84d56533

u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb Automotive Mobile LPDDR2 SDRAM

Features

List of Figures

Figure 1: 512Mb LPDDR2 Part Numbering ....................................................................................................... 2

Figure 2: 32 Meg x 16 I

DD61

Typical Self Refresh Current vs. Temperature .......................................................... 15

Figure 3: LPDDR2 x 1 Die ............................................................................................................................... 16

Figure 4: LPDDR2 x 2 Die ............................................................................................................................... 17

Figure 5: 121-Ball FBGA – 6.5mm x 8mm (Package Codes AB, FE) .................................................................... 18

Figure 6: 134-Ball FBGA – 10mm x 11.5mm (Package Code AC) ........................................................................ 19

Figure 7: 168-Ball PoP – 12mm x 12mm Single-Die (Package Code LG) ............................................................. 20

Figure 8: 121-Ball FBGA (x16) Ball Assignments .............................................................................................. 21

Figure 9: 134-Ball DDP FBGA (x32) Ball Assignments (Top View, Balls Down) ................................................... 22

Figure 10: 168-Ball PoP (x32) Ball Assignments ............................................................................................... 23

Figure 11: Functional Block Diagram ............................................................................................................. 25

Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 28

Figure 13: ACTIVATE Command .................................................................................................................... 40

Figure 14:

FAW Timing (8-Bank Devices) ....................................................................................................... 41

Figure 15: READ Output Timing –

DQSCK (MAX) ........................................................................................... 42

Figure 16: READ Output Timing –

DQSCK (MIN) ........................................................................................... 42

Figure 17: Burst READ – RL = 5, BL = 4,

DQSCK >

CK ..................................................................................... 43

Figure 18: Burst READ – RL = 3, BL = 8,

DQSCK <

CK ..................................................................................... 43

Figure 19:

DQSCKDL Timing ........................................................................................................................ 44

Figure 20:

DQSCKDM Timing ....................................................................................................................... 45

Figure 21:

DQSCKDS Timing ......................................................................................................................... 46

Figure 22: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 47

Figure 23: Seamless Burst READ – RL = 3, BL = 4,

CCD = 2 .............................................................................. 47

Figure 24: READ Burst Interrupt Example – RL = 3, BL = 8,

CCD = 2 ................................................................. 48

Figure 25: Data Input (WRITE) Timing ........................................................................................................... 49

Figure 26: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 49

Figure 27: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 50

Figure 28: Seamless Burst WRITE – WL = 1, BL = 4,

CCD = 2 ............................................................................ 50

Figure 29: WRITE Burst Interrupt Timing – WL = 1, BL = 8,

CCD = 2 ................................................................ 51

Figure 30: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 52

Figure 31: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 53

Figure 32: Data Mask Timing ......................................................................................................................... 53

Figure 33: Write Data Mask – Second Data Bit Masked .................................................................................... 54

Figure 34: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(

RTP(MIN)/

CK) = 2 ................................ 55

Figure 35: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 3 ................................ 56

Figure 36: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 57

Figure 37: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 2 ........................................ 58

Figure 38: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 59

Figure 39: Regular Distributed Refresh Pattern ............................................................................................... 63

Figure 40: Supported Transition from Repetitive REFRESH Burst .................................................................... 64

Figure 41: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 65

Figure 42: Recommended Self Refresh Entry and Exit ..................................................................................... 66

Figure 43:

SRF Definition .............................................................................................................................. 67

Figure 44: All-Bank REFRESH Operation ........................................................................................................ 67

Figure 45: Per-Bank REFRESH Operation ....................................................................................................... 68

Figure 46: SELF REFRESH Operation .............................................................................................................. 69

Figure 47: MRR Timing – RL = 3,

MRR = 2 ...................................................................................................... 71

Figure 48: READ to MRR Timing – RL = 3,

MRR = 2 ......................................................................................... 72

Figure 49: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 73

Figure 50: Temperature Sensor Timing ........................................................................................................... 75

PDF: 09005aef84d56533

u67m_512mb_aat-ait_mobile_lpddr2.pdf - Rev. J 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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