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MT46V16M16CY-5B AIT:M TR

Description
SDRAM - DDR 存储器 IC 256Mb(16M x 16) 并联 200 MHz 700 ps 60-FBGA(8x12.5)
Categorysemiconductor    memory   
File Size1MB,91 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT46V16M16CY-5B AIT:M TR Overview

SDRAM - DDR 存储器 IC 256Mb(16M x 16) 并联 200 MHz 700 ps 60-FBGA(8x12.5)

MT46V16M16CY-5B AIT:M TR Parametric

Parameter NameAttribute value
category
MakerMicron Technology
seriesAutomotive, AEC-Q100
PackageTape and Reel (TR)
memory typeVolatile
memory formatDRAM
technologySDRAM - DDR
storage256Mb(16M x 16)
memory interfacein parallel
Write cycle time - words, pages15ns
Voltage - Power supply2.3V ~ 2.7V
Operating temperature-40°C ~ 85°C(TA)
Installation typesurface mount type
Package/casing60-TFBGA
Supplier device packaging60-FBGA(8x12.5)
Clock frequency200 MHz
interview time700 ps
Basic product numberMT46V16M16
256Mb: x8, x16 Automotive DDR SDRAM
Features
Automotive DDR SDRAM
MT46V32M8 – 8 Meg x 8 x 4 banks
MT46V16M16 – 4 Meg x 16 x 4 banks
Features
• V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
V
DD
= 2.6V ±0.1V, V
DDQ
= 2.6V ±0.1V (DDR400)
1
• Bidirectional data strobe (DQS) transmitted/
received with data, that is, source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths (BL): 2, 4, or 8
• Auto refresh
64ms, 8192-cycle(AIT)
16ms, 8192-cycle (AAT)
• Self refresh (not available on AAT devices)
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2-compatible)
• Concurrent auto precharge option supported
t
RAS lockout supported (
t
RAP =
t
RCD)
• AEC-Q100
• PPAP submission
• 8D response time
Options
• Configuration
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic package – OCPL
66-pin TSOP
66-pin TSOP (Pb-free)
• Plastic package
60-ball FBGA (8mm x 12.5mm)
60-ball FBGA (8mm x 12.5mm)
(Pb-free)
• Timing – cycle time
5ns @ CL = 3 (DDR400)
• Self refresh
Standard
Low-power self refresh
• Temperature rating
Industrial (–40qC to +85qC)
Automotive (–40qC to +105qC)
• Revision
x8, x16
Marking
32M8
16M16
TG
P
CV
CY
-5B
None
L
AIT
AAT
:M
Notes: 1. DDR400 devices operating at < DDR333 con-
ditions can use V
DD
/V
DDQ
= 2.5V +0.2V.
2. Not all options listed can be combined to
define an offered product. Use the Part Cata-
log Search on www.micron.com for product
offerings and availability.
PDF:09005aef848ea6ef/Source: 09005aef845d3b9c
256mb_x8x16_at_ddr_t66a_d1.fm - Rev. A; Core DDR Rev.
C 7/18EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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