MT41K256M4DA-107:J datasheet, PDF

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MT41K256M4DA-107:J: DescriptionSDRAM - DDR3 存储器 IC 1Gb（256M x 4）并联 933 MHz 20 ns 78-FBGA（8x10.5）; Categorysemiconductor memory; File Size455KB，21 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT41K256M4DA-107:J Overview

SDRAM - DDR3 存储器 IC 1Gb（256M x 4）并联 933 MHz 20 ns 78-FBGA（8x10.5）

MT41K256M4DA-107:J Parametric

Parameter Name	Attribute value
category
Maker	Micron Technology
series	-
Package	tray
memory type	Volatile
memory format	DRAM
technology	SDRAM - DDR3
storage	1Gb（256M x 4）
memory interface	in parallel
Write cycle time - words, pages	-
Voltage - Power supply	1.283V ~ 1.45V
Operating temperature	0°C ~ 95°C（TC）
Installation type	surface mount type
Package/casing	78-TFBGA
Supplier device packaging	78-FBGA（8x10.5）
Clock frequency	933 MHz
interview time	20 ns
Basic product number	MT41K256M4

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1Gb: x4, x8, x16 DDR3L SDRAM Addendum

Description

1.35V DDR3L SDRAM Addendum

MT41K256M4 – 32 Meg x 4 x 8 banks

MT41K128M8 – 16 Meg x 8 x 8 banks

MT41K64M16 – 8 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of the

DDR3 SDRAM (1.5V). Unless stated otherwise, DDR3L

SDRAM meets the functional and timing specifica-

tions listed in the equivalent density DDR3 SDRAM

data sheet located on www.micron.com.

•

of 0°C to 95°C

–

64ms, 8192-cycle refresh at 0°C to 85°C

–

32ms at 85°C to 95°C

•

Self refresh temperature (SRT)

•

Automatic self refresh (ASR)

•

Write leveling

•

Multipurpose register

•

Output driver calibration

Features

•

= V

DDQ

= +1.35V (1.283V to 1.45V)

Backward compatible to V

= V

DDQ

= 1.5V ±0.075V

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

Programmable CAS (READ) latency (CL)

Programmable CAS additive latency (AL)

Programmable CAS (WRITE) latency (CWL)

Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Self refresh mode

Options

•

Configuration

–

256 Meg x 4

–

128 Meg x 8

–

64 Meg x 16

•

FBGA package (Pb-free) – x4, x8

–

78-ball FBGA (8mm x 11.5mm) Rev. F, G

•

FBGA package (Pb-free) – x16

–

96-ball FBGA (8mm x 14mm) Rev. G

•

Timing – cycle time

–

1.25ns @ CL = 11 (DDR3-1600)

–

1.5ns @ CL = 9 (DDR3-1333)

•

Revision

Note:

Marking

256M4

128M8

64M16

-125

-15E

:F, :G

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on

http://www.micron.com

for available offerings.

Table 1: Key Timing Parameters

Speed Grade

-125

-15E

-187E

Note:

Data Rate (MT/s)

1600

1333

1066

Target

RCD-

RP-CL (ns)

11-11-11

9-9-9

7-7-7

RCD

(ns)

CL (ns)

13.75

13.5

13.1

13.75

13.5

13.1

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

Table 2: Addressing

Parameter

Configuration

Refresh count

Row address

256 Meg x 4

32 Meg x 4 x 8 banks

16K A[13:0]

128 Meg x 8

16 Meg x 8 x 8 banks

16K A[13:0]

64 Meg x 16

4 Meg x 16 x 8 banks

8K A[12:0]

PDF: 09005aef833b7221

1Gb_1_35V_DDR3L.pdf - Rev. F 2/11 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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