RS8228/M28228
Octal ATM Transmission Convergence PHY Device
The RS8228 Octal ATM Transmission Convergence PHY device dramatically improves
performance for switch and access system low-speed ports by integrating all the ATM
physical layer processing functions found in the ATM Forum Cell Based Transmission
Convergence Sublayer specification (af-phy-0043.000) for eight individual ports. Each
port can be independently configured for operation at speeds ranging from 64 kbps to
52 Mbps. There is also a powerdown mode option for each TC port. A UTOPIA Level 2
Multi-PHY interface connects the device to the host switch or terminal system and
concentrates the ATM cell traffic onto one interface.
Typical system implementations center around the concentration of ATM cells over
standard PDH data rates such as T1/E1 lines, DS3/E3 lines, and multiple Digital
Subscriber Line (DSL) formats such as HDSL, ADSL or VDSL*. For each format,
external devices perform the appropriate Physical Media Dependent (PMD) layer
functions and present the RS8228 with a payload bit stream. The RS8228 then performs
all cell alignment functions on that bit stream. This gives system designers a simple,
modular, and low-cost architecture for supporting all UNI and NNI ATM interfaces below
52 Mbps. Because the RS8228 performs only the cell-based portion of the protocol
stack, designers can select the most integrated framer and Line Interface Unit (LIU)
available or reuse existing devices and software.
The RS8228 can also be used in combination with a Conexant Segmentation and
Reassembly (SAR) device. The RS8228 gluelessly connects to the SAR via the UTOPIA
and microprocessor interfaces. The device can be configured and controlled optionally
through a generic microprocessor interface. The RS8228’s chip-select feature allows
the microprocessor to select any of the framers through the PHY. The RS8228’s eight
interrupt inputs provide an internal mechanism for registering and controlling generated
interrupts.
* The term xDSL is used throughout this document to refer to the various DSL
formats as a group.
Distinguishing Features
•
•
8 cell-based TC Ports
UTOPIA interface
– Level 2
– 8/16 bit modes
– Multi-PHY
– Redundant channel
Glueless interface to Conexant’s:
– T1/E1 framers
– T3/E3 framers
– HDSL/SDSL devices
– SAR devices
Software reference material provided
8 chip selects for external framers
8 interrupt inputs for external
framers
Octet- and bit-level cell delineation
ITU I.432-compliant
Available in either 27 mm or 17 mm
BGA packages
•
•
•
•
•
•
•
Functional Block Diagram
Host
RS8228
LCs[7]
LCs[0]
LInt~[7]
LInt~[0]
Interrupt
Status
Microprocessor Interface
UTOPIA
Level 2
Multi-PHY
Tx/Rx FIFO
4 Cells
ATM
Layer
Device
8/16
UTOPIA
Level 2
Interface
External
PMD
or
Framer
Framer
(Line)
Interface
External
PMD
or
Framer
Cell Processor
Line
Interface
Port 0
G.804 Cell Framer
Cell Processor
Line
Interface
Port 7
G.804 Cell Framer
Tx/Rx FIFO
4 Cells
28228-DSH-001-C
Mindspeed Technologies
™
Mindspeed Proprietary and Confidential
April 2005
Ordering Information
Model Number
RS8228EBG
RS8228EBGB
M28228
Manufacturing
Part Number
28228-11
28228-12
28228-21
Product
Revision
A
B
A
Package
272-ball, 27 mm BGA
272-ball, 27 mm BGA
256-ball, 17 mm BGA
Operating Temperature
–40
°
C to 85
°
C
–40
°
C to 85
°
C
–40
°
C to 85
°
C
Revision History
Revision
C
B
A
Level
—
—
—
Date
April 2005
November 2003
November 2001
Description
Corrected
0x05—IOMODE (Input/Output Mode Control Register),
bits 5 and 3.
Placed registers in numerical order.
This version has the 17 mm BGA information included. Note that
this document was previously released under the document
numbers 100064A and 100064B.
© 2005 Mindspeed Technologies
TM
, Inc. All rights reserved.
Information in this document is provided in connection with Mindspeed Technologies
TM
("Mindspeed
TM
") products.
These materials are provided by Mindspeed as a service to its customers and may be used for informational pur-
poses only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any sepa-
rate agreement related to this document, Mindspeed assumes no liability whatsoever. Mindspeed assumes no
responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications and prod-
uct descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall
have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications
and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted by this document.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR
IMPLIED, RELATING TO SALE AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WAR-
RANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL
DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLEC-
TUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETE-
NESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE
MATERIALS. MINDSPEED SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSE-
QUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH
MAY RESULT FROM THE USE OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed cus-
tomers using or selling Mindspeed products for use in such applications do so at their own risk and agree to fully
indemnify Mindspeed for any damages resulting from such improper use or sale.
28228-DSH-001-C
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
Framer (Line) Interface Section
•
•
Programmable bit or byte synchronous serial interface
Direct connection to external Conexant components for:
– T1/E1
– DS3
– E3
– J2
– xDSL
– General purpose mode
– Interrupt and chip select signals for each external framer
•
Multi-PHY capability
Control and Status
Microprocessor Interface
•
•
•
•
•
•
•
•
Asynchronous SRAM-like interface mode
Synchronous, glueless Bt8233/RS8234 SAR interface mode
8-bit data bus
Open-drain interrupt output
Open-drain ready output
8–50 MHz operation
All control registers are read/write
Four programmable status indicator signals per port
Cell Alignment Framing Section
•
Supports ATM cell interface for:
– Circuit-based physical layer
– Cell-based physical layer
Passes or rejects idle cells or selected cells based on header
register configuration
Recovers cell alignment from Header Error Correction (HEC)
Performs single-bit HEC correction and single- or multiple-bit
detection
Generates cell status bits, cell counts, and error counts
Inserts headers and generates HEC
Inserts idle cells when no traffic is ready
•
•
•
•
•
•
Counters/Status Register Section
•
•
•
•
Summary interrupt indications
Configuration of interrupt enables
One-second counter latching
Counters for:
– LOCD events
– Corrected HEC errors
– Uncorrected HEC errors
– Transmitted cells
– Matching received cells
– Non-matching received cells
UTOPIA Level 2 Interface
•
•
•
PHY cell to UTOPIA interface
50 MHz maximum clock rate
8/16-bit data path interface
28228-DSH-001-C
Mindspeed Technologies
™
Mindspeed Proprietary and Confidential
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .viii
1.0 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
1.5
Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
27 mm Pin Diagram and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
17 mm Pin Diagram and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Block Diagram and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
ATM Cell Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2.1.1
ATM Cell Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
2.1.1.1
HEC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.1.2
ATM Cell Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.0.0.1
Cell Delineation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.0.0.2
Cell Screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1.3
Cell Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.0.0.1
SSS Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.0.0.2
DSS Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Framing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2.1
T1/E1 Timing for the CX28229 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2.2
DS3 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2.3
E3/G.832 34.368 Mbps Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2.4
J2 6.312 Mbps Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.2.5
General Purpose Mode Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.3.1
UTOPIA Transmit and Receive FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.3.2
UTOPIA 8-bit and 16-bit Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.3.3
UTOPIA Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3.4
UTOPIA Multi-PHY Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3.5
UTOPIA Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.3.6
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4.1
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4.2
Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4.3
Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.4.4
One-second Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2
2.3
2.4
28228-DSH-001-C
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Mindspeed Proprietary and Confidential
iv
2.4.5
2.4.6
2.5
External Framer Interrupts and Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.0.0.1
Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.4.6.1
Interrupt Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Source Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
0x00—SUMINT (Summary Interrupt Indication Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
0x01—ENSUMINT (Summary Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
0x04—PMODE (Port Mode Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
0x05—IOMODE (Input/Output Mode Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
0x06—VERSION (Part Number/Version Status Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
0x07—OUTSTAT (Output Pin Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
0x08—CGEN (Cell Generation Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
0x09—HDRFIELD (Header Field Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
0x0A—IDLPAY (Transmit Idle Cell Payload Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
0x0B—ERRPAT (Error Pattern Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
0x0C—CVAL (Cell Validation Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
0x0D—UTOP1 (UTOPIA Control Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
0x0E—UTOP2 (UTOPIA Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
0x10—TXHDR1 (Transmit Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
0x11—TXHDR2 (Transmit Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
0x12—TXHDR3 (Transmit Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
0x13—TXHDR4 (Transmit Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
0x14—TXIDL1 (Transmit Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
0x15—TXIDL2 (Transmit Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
0x16—TXIDL3 (Transmit Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
0x17—TXIDL4 (Transmit Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
0x18—RXHDR1 (Receive Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
0x19—RXHDR2 (Receive Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
0x1A—RXHDR3 (Receive Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
0x1B—RXHDR4 (Receive Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
0x1C—RXMSK1 (Receive Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
0x1D—RXMSK2 (Receive Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
0x1E—RXMSK3 (Receive Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
0x1F—RXMSK4 (Receive Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
0x20—RXIDL1 (Receive Idle Cell Header Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
0x21—RXIDL2 (Receive Idle Cell Header Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
0x22—RXIDL3 (Receive Idle Cell Header Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
0x23—RXIDL4 (Receive Idle Cell Header Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
0x24—IDLMSK1 (Receive Idle Cell Mask Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
0x25—IDLMSK2 (Receive Idle Cell Mask Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
0x26—IDLMSK3 (Receive Idle Cell Mask Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
0x27—IDLMSK4 (Receive Idle Cell Mask Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
0x28—ENCELLT (Transmit Cell Interrupt Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
0x29—ENCELLR (Receive Cell Interrupt Control Register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
28228-DSH-001-C
Mindspeed Technologies™
Mindspeed Proprietary and Confidential
v
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