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MT41K64M16TW-107 AAT:J

Description
SDRAM - DDR3L 存储器 IC 1Gb 并联 933 MHz 20 ns 96-FBGA(8x14)
Categorysemiconductor    memory   
File Size3MB,209 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT41K64M16TW-107 AAT:J Overview

SDRAM - DDR3L 存储器 IC 1Gb 并联 933 MHz 20 ns 96-FBGA(8x14)

MT41K64M16TW-107 AAT:J Parametric

Parameter NameAttribute value
category
MakerMicron Technology
seriesAutomotive, AEC-Q100
PackageBulk
memory typeVolatile
memory formatDRAM
technologySDRAM - DDR3L
storage1Gb
memory organization64M x 16
memory interfacein parallel
Clock frequency933 MHz
Write cycle time - words, pages-
interview time20 ns
Voltage - Power supply1.283V ~ 1.45V
Operating temperature-40°C ~ 105°C(TC)
Installation typesurface mount type
Package/casing96-TFBGA
Supplier device packaging96-FBGA(8x14)
Basic product numberMT41K64M16
1Gb: x8, x16 Automotive DDR3L SDRAM
Description
Automotive DDR3L SDRAM
MT41K128M8 – 16 Meg x 8 x 8 banks
MT41K64M16 – 8 Meg x 16 x 8 banks
Description
The 1.35V DDR3L SDRAM device is a low-voltage ver-
sion of the 1.5V DDR3 SDRAM device. Refer to the
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
Write leveling
Multipurpose register
Output driver calibration
AEC-Q100
PPAP submission
8D response time
Features
V
DD
= V
DDQ
= +1.35V (1.283V to 1.45V)
Backward compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of -40°C to 105°C
– 64ms, 8192-cycle refresh at -40°C to 85°C
– 32ms at 85°C to 105°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Options
1
• Configuration
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) – x8
– 78-ball FBGA (8mm x 10.5mm)
• FBGA package (Pb-free) – x16
– 96-ball FBGA (8mm x 14mm)
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40°C T
C
+95°C)
– Automotive (–40°C T
C
+105°C)
• Revision
Notes:
Marking
128M8
64M16
DA
TW
-107
A
IT
AT
:J
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2. The datasheet does not support ×4 mode
even though ×4 mode description exists in
the following sections.
Table 1: Key Timing Parameters
Speed Grade
-107
Data Rate (MT/s)
1866
Target
t
RCD-
t
RP-CL
13-13-13
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.91
13.91
Table 2: Addressing
Parameter
Configuration
Refresh count
128 Meg x 8
16 Meg x 8 x 8 banks
8K
64 Meg x 16
8 Meg x 16 x 8 banks
8K
PDF: 09005aef85e0b6f6
1Gb_automotive_DDR3L_F.pdf - Rev. C 5/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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