High-Current, High &
Low-Side, Gate-Drive IC
FAN7390
Description
The FAN7390 is a monolithic high− and low−side gate−drive IC,
which can drive high speed MOSFETs and IGBTs that operate up to
+600 V. It has a buffered output stage with all NMOS transistors
designed for high pulse current driving capability and minimum
cross−conduction.
ON Semiconductor’s high−voltage process and common−mode
noise canceling techniques provide stable operation of the high−side
driver under high dv/dt noise circumstances. An advanced level shift
circuit offers high−side gate driver operation up to V
S
=
−9.8
V
(typical) for V
BS
= 15 V.
The UVLO circuit prevents malfunction when V
DD
and V
BS
are
lower than the specified threshold voltage.
The high current and low output voltage drop feature make this
device suitable for the PDP sustain pulse driver, motor driver,
switching power supply, and high− power DC−DC converter
applications.
Features
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SOIC8
8−SOP
CASE 751EG
SOIC14
14−SOP
CASE 751ER
MARKING DIAGRAM
7390
ALYW
FAN7390MX
7390,
FAN7390
A
L
YW
&Z
&3
&K
= Device Code
= Assembly Site
= Wafer Lot Number
= Assembly Start Week
= Assembly Plant Code
= 3−Digit Date Code
= 2−Digits Lot Run Traceability Code
FAN7390
&Z&3&K
FAN7390M1X
•
Floating Channels for Bootstrap Operation to +600 V
•
Typically 4.5 A / 4.5 A Sourcing / Sinking Current Driving
•
•
•
•
•
•
•
•
•
•
•
Capability
Common−Mode dv/dt Noise−Canceling Circuit
Built−in Under−Voltage Lockout for Both Channels
Matched Propagation Delay for Both Channels
Logic (V
SS
) and Power (COM) Ground
±7
V Offset
3.3 V and 5 V Input Logic Compatible
Output In−Phase with Input
This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Applications
PDP Sustain Driver
HID Lamp Ballast
SMPS
Motor Driver
©
Semiconductor Components Industries, LLC, 2008
May, 2021
−
Rev. 2
1
Publication Order Number:
FAN7390/D
FAN7390
TYPICAL APPLICATION CIRCUIT
15 V
R
BOOT
D
BOOT
HIN
Controller
LIN
2
LIN
HO
7
C
BOOT
3
COM
V
S
6
OUTPUT
4
LO
V
DD
5
C1
R3
R4
Q2
Load
1
HIN
V
B
8
R1
Q1
R2
Up to 600 V
FAN7390
Figure 1. Application Circuit for Half−Bridge (Referenced 8−SOP)
15V
R
BOOT
D
BOOT
FAN7390M1
HIN
Controller
V
SS
LIN
2
3
4
5
6
7
C1
LIN
V
SS
NC
COM
LO
V
DD
V
B
13
HO 12
V
S
11
NC 10
NC 9
NC
8
R3
R4
Q2
OUTPUT
Load
R1
C
BOOT
Q1
R2
1
HIN
NC 14
Up to 600 V
Figure 2. Application Circuit for Half−Bridge (Referenced 14−SOP)
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2
FAN7390
INTERNAL BLOCK DIAGRAM
FAN7390
UVLO
DRIVER
8
V
B
PULSE
GENERATOR
HIN
1
200 kW
NOISE
CANCELLER
R
S
R
Q
7
HO
6
V
S
5
UVLO
V
SS
/COM
LEVEL
SHIFT
DRIVER
V
DD
LIN
2
200 kW
DELAY
4
LO
3
COM
Figure 3. Functional Block Diagram (Referenced 8−SOP)
FAN7390M1
UVLO
DRIVER
13
V
B
PULSE
GENERATOR
HIN
1
200 kW
NOISE
CANCELLER
R
S
R
Q
12
HO
11
V
S
7
UVLO
DRIVER
V
DD
LIN
2
200 kW
DELAY
V
SS
/COM
LEVEL
SHIFT
6
LO
V
SS
3
Pin 4, 8, 9, 10 and 14 are no connection
5
COM
Figure 4. Functional Block Diagram (Referenced 14−SOP)
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FAN7390
PIN CONFIGURATION
FAN7390M
FAN7390M1
HIN
LIN
COM
LO
1
2
FAN7390
3
4
8
7
6
5
V
B
HO
V
S
V
DD
HIN
LIN
V
SS
NC
COM
LO
V
DD
1
2
3
4
5
6
7
FAN7390M1
14
13
12
11
10
9
8
NC
V
B
HO
V
S
NC
NC
NC
Figure 5. Pin Assignments (Top View)
PIN DEFINITIONS
8−Pin
1
2
14−Pin
1
2
3
3
4
5
6
7
8
5
6
7
11
12
13
4, 8, 9, 10, 14
Name
HIN
LIN
V
SS
COM
LO
V
DD
V
S
HO
V
B
NC
Description
Logic Input for High−Side Gate Driver Output
Logic Input for Low−Side Gate Driver Output
Logic Ground (FAN7390M1 only)
Low−Side Driver Return
Low−Side Driver Output
Low−Side and Logic Part Supply Voltage
High−Voltage Floating Supply Return
High−Side Driver Output
High−Side Floating Supply
No Connect
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FAN7390
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C, unless otherwise noted)
Symbol
V
S
V
B
V
HO
V
DD
V
LO
V
IN
V
SS
dV
S
/dt
P
D
(Note 1, 2, 3)
q
JA
T
J
T
STG
Characteristics
High−Side Floating Supply Offset Voltage
High−Side Floating Supply Voltage
High−Side Floating Output Voltage HO
Low−Side and Logic Fixed Supply Voltage
Low−Side Output Voltage LO
Logic Input Voltage (HIN and LIN)
Logic Ground (FAN7390M1 only)
Allowable Offset Voltage Slew Rate
Power Dissipation
Min
V
B
−
25
−0.3
V
S
−
0.3
−0.3
−0.3
V
SS
−
0.3
V
DD
−
25
−
8−SOP
14−SOP
Thermal Resistance, Junction−to−Ambient
8−SOP
14−SOP
Junction Temperature
Storage Temperature
−
−
Max
V
B
+ 0.3
625.0
V
B
+ 0.3
25.0
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
50
0.625
1.000
200
110
+150
+150
°C
°C
°C/W
Unit
V
V
V
V
V
V
V
V/ns
W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material).
2. Refer to the following standards:
JESD51−2: Integral circuits thermal test method environmental conditions
−
natural convection
JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages.
3. Do not exceed P
D
under any circumstances.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
B
V
S
V
HO
V
DD
V
LO
V
IN
T
A
Parameter
High−Side Floating Supply Voltage
High−Side Floating Supply Offset Voltage
High−Side Output Voltage
Low−Side and Logic Supply Voltage
Low−Side Output Voltage
Logic Input Voltage (HIN and LIN)
Operating Ambient Temperature
Min
V
S
+ 10
6
−
V
DD
V
S
10
COM
V
SS
−40
Max
V
S
+ 22
600
V
B
22
V
DD
V
DD
+125
Unit
V
V
V
V
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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