511BBA250M000AAG datasheet, PDF

511BBA250M000AAG: Description振荡器 250 MHz LVDS XO（标准） 3.3V 启用/禁用 6-SMD，无引线; CategoryPassive components oscillator; File Size427KB，31 Pages; ManufacturerSilicon Labs; Websitehttps://www.silabs.com

Download Datasheet Parametric View All

511BBA250M000AAG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	511BBA250M000AAG	-	-	View	Buy Now

振荡器 250 MHz LVDS XO（标准） 3.3V 启用/禁用 6-SMD，无引线

Parameter Name	Attribute value
category
Maker	Silicon Labs
series	Si511
Package	bring
basic resonator	crystal
type	XO (Standard)
Function	enable/disable
output	LVDS
Voltage - Power supply	3.3V
frequency stability	±25ppm
绝对牵引范围 (APR)	-
Operating temperature	-40°C ~ 85°C
spread spectrum bandwidth	-
Current - Power Supply (Maximum)	23mA
grade	-
Installation type	surface mount type
Package/casing	6-SMD, no leads
size/dimensions	0.276" long x 0.197" wide (7.00mm x 5.00mm)
Height - Installation (maximum)	0.071"（1.80mm）
电流 - 供电（禁用）（最大值）	18mA
frequency	250 MHz
Basic product number	SI511

How to select the I/O standard in the Quartus configuration pin?: Help: When configuring pins with Quartus, how do I select the I/O standard in the pin planner? The voltage is configured according to the hardware input voltage in the bank, but how do I select the su...; 李豆芽 FPGA/CPLD

Evaluation and Application of Class D Audio Power Amplifiers: Among the basic amplifier topologies, class AB amplifiers have been widely used in various audio products, including mobile phones, mp3 players and PMP systems. Considering that class AB amplifiers ca...; feifei Analog electronics

EV2400 WIN7 64 BQ20Z45: Win7 64-bit, installed Bq20Z45R1, connected EV2400, the hardware properties show USB input device, can be updated to V0.28 through update. But the software reports an error, can not connect the batter...; qwqwqw2088 Analogue and Mixed Signal

Driver project for serial port chip 16550 using 2416 (2450) under wince-----Help!: Dear friends: I have the following project: Serial port driver based on S3C2416, serial port chip 16550, now there is MDD+PDD (middle layer) but lacks the lowest layer initialization code for 16550. D...; tt181003 Embedded System

Digital clock display based on FPGA: Using Verilog HDL language, I can display a needle-type digital clock on LCD through VGA, just like the clock in the date and time properties in the lower right corner of Windows. What I want to ask i...; goodbey155 FPGA/CPLD

Regarding the Hook ZwReadFile issue.: NTSTATUS NewNtReadFile( IN HANDLEFileHandle,IN HANDLEEventOPTIONAL,IN PIO_APC_ROUTINEApcRoutineOPTIONAL,IN PVOIDApcContextOPTIONAL,OUT PIO_STATUS_BLOCKIoStatusBlock,OUT PVOIDBuffer,IN ULONGLength,IN P...; sucuiqin Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components