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DM74AS161N

Description
AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16
Categorylogic    logic   
File Size66KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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DM74AS161N Overview

AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16

DM74AS161N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeDIP
package instruction0.300 INCH, MS-001, PLASTIC, DIP-16
Contacts16
Reach Compliance Codeunknow
Is SamacsysN
Counting directionUP
seriesAS
JESD-30 codeR-PDIP-T16
length19.304 mm
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Maximum Frequency@Nom-Su75000000 Hz
MaximumI(ol)0.02 A
Operating modeSYNCHRONOUS
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)53 mA
propagation delay (tpd)13 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax75 MHz
Base Number Matches1
DM74AS161 • DM74AS163 Synchronous 4-Bit Counter with Asynchronous Clear • Synchronous 4-Bit Counter
April 1984
Revised March 2000
DM74AS161 • DM74AS163
Synchronous 4-Bit Counter with Asynchronous Clear •
Synchronous 4-Bit Counter
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for application in high speed counting
designs. The DM74AS161 and DM74AS163 are 4-bit
binary counters. The DM74AS161 clear asynchronously,
while the DM74AS163 clear synchronously. The carry out-
put is decoded to prevent spikes during normal counting
mode of operation. Synchronous operation is provided by
having all flip-flops clocked simultaneously so that outputs
change coincident with each other when so instructed by
count enable inputs and internal gating. This mode of oper-
ation eliminates the output counting spikes which are nor-
mally associated with asynchronous (ripple clock)
counters. A buffered clock input triggers the four flip-flops
on the rising (positive-going) edge of the clock input wave-
form.
These counters are fully programmable, that is, the outputs
may each be preset to either level. As presetting is syn-
chronous, setting up a low level at the LOAD input disables
the counter and causes the outputs to agree with set up
data after the next clock pulse regardless of the levels of
enable input. LOW-to-HIGH transitions at the LOAD input
are perfectly acceptable regardless of the logic levels on
the clock or enable inputs.
The DM74AS161 clear function is asynchronous. A low
level at the clear input sets all four of the flip-flop outputs
LOW regardless of the levels of clock, load or enable
inputs. This counter is provided with a clear on power-up
feature. The DM74AS163 clear function is synchronous;
and a low level at the clear input sets all four of the flip-flop
outputs LOW after the next clock pulse, regardless of the
levels of enable inputs. This synchronous clear allows the
count length to be modified easily, as decoding the maxi-
mum count desired can be accomplished with one external
NAND gate. The gate output is connected to the clear input
to synchronously clear the counter to all LOW outputs.
LOW-to-HIGH transitions at the clear input of the
DM74AS163 is also permissible regardless of the levels of
logic on the clock, enable or load inputs.
The carry look ahead circuitry provides for cascading
counters for n bit synchronous application without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs (P and T) and a ripple carry
output. Both count-enable inputs must be HIGH to count.
The T input is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high
level output pulse with a duration approximately equal to
the high level portion of QA output. This high level overflow
ripple carry pulse can be used to enable successive cas-
caded stages. HIGH-to-LOW level transitions at the enable
P or T inputs of the DM74AS161 and DM74AS163, may
occur regardless of the logic level on the clock.
The DM74AS161 and DM74AS163 feature a fully indepen-
dent clock circuit. Changes made to control inputs (enable
P or T, or load) that will modify the operating mode will
have no effect until clocking occurs. The function of the
counter (whether enabled, disabled, loading or counting)
will be dictated solely by the conditions meeting the stable
set-up and hold times.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s
Improved AC performance over Schottky and low power
Schottky counterparts
s
Synchronously programmable
s
Internal look ahead for fast counting
s
Carry output for n-bit cascading
s
Synchronous counting
s
Load control line
s
ESD inputs
Ordering Code:
Order Number
DM74AS161M
DM74AS161N
DM74AS163M
DM74AS163N
Package Number
M16A
N16E
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS006291
www.fairchildsemi.com

DM74AS161N Related Products

DM74AS161N DM74AS161 DM74AS161M DM74AS163M DM74AS163N
Description AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 AS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
Counting direction UP UP UP UP UP
series AS AS AS AS AS
Operating mode SYNCHRONOUS SYN SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Number of digits 4 4 4 4 4
Number of functions 1 1 1 1 1
Number of terminals 16 16 16 16 16
Maximum operating temperature 70 °C 70 Cel 70 °C 70 °C 70 °C
surface mount NO Yes YES YES NO
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE GULL WING GULL WING GULL WING THROUGH-HOLE
Terminal location DUAL pair DUAL DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE edge POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
Is it Rohs certified? conform to - conform to conform to conform to
Maker Fairchild - Fairchild Fairchild Fairchild
Parts packaging code DIP - SOIC SOIC DIP
package instruction 0.300 INCH, MS-001, PLASTIC, DIP-16 - 0.150 INCH, MS-012, SOIC-16 0.150 INCH, MS-012, SOIC-16 0.300 INCH, MS-001, PLASTIC, DIP-16
Contacts 16 - 16 16 16
Reach Compliance Code unknow - unknow unknow unknow
Is Samacsys N - N N N
JESD-30 code R-PDIP-T16 - R-PDSO-G16 R-PDSO-G16 R-PDIP-T16
length 19.304 mm - 9.9 mm 9.9 mm 19.304 mm
Load/preset input YES - YES YES YES
Logic integrated circuit type BINARY COUNTER - BINARY COUNTER BINARY COUNTER BINARY COUNTER
Maximum Frequency@Nom-Su 75000000 Hz - 75000000 Hz 75000000 Hz 75000000 Hz
MaximumI(ol) 0.02 A - 0.02 A 0.02 A 0.02 A
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP - SOP SOP DIP
Encapsulate equivalent code DIP16,.3 - SOP16,.25 SOP16,.25 DIP16,.3
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE - SMALL OUTLINE SMALL OUTLINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - 260 260 NOT SPECIFIED
power supply 5 V - 5 V 5 V 5 V
Maximum supply current (ICC) 53 mA - 53 mA 53 mA 53 mA
propagation delay (tpd) 13 ns - 13 ns 13 ns 13 ns
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified
Maximum seat height 5.08 mm - 1.75 mm 1.75 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V 5 V 5 V
technology TTL - TTL TTL TTL
Terminal pitch 2.54 mm - 1.27 mm 1.27 mm 2.54 mm
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 7.62 mm - 3.9 mm 3.9 mm 7.62 mm
minfmax 75 MHz - 75 MHz 75 MHz 75 MHz
Base Number Matches 1 - 1 1 1
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