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M74HC4514TTR

Description
4 TO 16 LINE DECODER/LATCH
Categorylogic    logic   
File Size199KB,12 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Download Datasheet Parametric Compare View All

M74HC4514TTR Overview

4 TO 16 LINE DECODER/LATCH

M74HC4514TTR Parametric

Parameter NameAttribute value
MakerSTMicroelectronics
Parts packaging codeTSSOP
package instructionTSSOP-24
Contacts24
Reach Compliance Codeunknow
ECCN codeEAR99
seriesHC/UH
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G24
length7.8 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeOTHER DECODER/DRIVER
MaximumI(ol)0.004 A
Number of functions1
Number of terminals24
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
power supply2/6 V
Prop。Delay @ Nom-Su56 ns
propagation delay (tpd)230 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm
M74HC4514
4 TO 16 LINE DECODER/LATCH
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 20 ns (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 4514
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HC4514B1R
M74HC4514M1R
T&R
M74HC4514RM13TR
M74HC4514TTR
DESCRIPTION
The M74HC4514 is an high speed CMOS 4 LINE
TO 16 LINE SEGMENT DECODER WITH
LATCHED INPUTS fabricated with silicon gate
C
2
MOS technology.
A binary code stored in the four input latches (A to
D) provides a high level at the selected one of
sixteen outputs excluding the other fifteen outputs,
when the inhibit input (INHIBIT) is held low. When
the inhibit input (INHIBIT) is held high, all outputs
are kept low level, while the latch function is
available. The data applied to the data inputs are
transferred to the Q outputs of latches when the
strobe input is held high. When the strobe input is
taken low, the information data applied to the data
input at a time is retained at the output of the
latches.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2003
1/12

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