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DM74AS573N

Description
Octal D-Type Transparent Latch with 3-STATE Outputs
Categorylogic    logic   
File Size54KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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DM74AS573N Overview

Octal D-Type Transparent Latch with 3-STATE Outputs

DM74AS573N Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Parts packaging codeDIP
package instructionDIP, DIP20,.3
Contacts20
Reach Compliance Codeunknow
seriesAS
JESD-30 codeR-PDIP-T20
JESD-609 codee3
length26.075 mm
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.048 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT APPLICABLE
power supply5 V
Maximum supply current (ICC)106 mA
Prop。Delay @ Nom-Su6 ns
propagation delay (tpd)6 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT APPLICABLE
width7.62 mm
Base Number Matches1
DM74AS573 Octal D-Type Transparent Latch with 3-STATE Outputs
October 1986
Revised March 2000
DM74AS573
Octal D-Type Transparent Latch with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased HIGH-logic-level drive provide these registers
with the capability of being connected directly to and driv-
ing the bus lines in a bus-organized system without need
for interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The eight latches of the DM74AS573 are transparent D-
type latches, meaning that while the enable (G) is HIGH
the Q outputs will follow the data (D) inputs. When the
enable is taken LOW the output will be latched at the level
of the data that was set UP.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
The pin-out is arranged to ease printed circuit board layout.
All data inputs are on one side of the package while all the
outputs are on the other side.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Functionally equivalent with DM74S373
s
Improved AC performance over DM74S373 at approxi-
mately half the power
s
3-STATE buffer-type outputs drive bus lines directly
s
Bus structured pinout
Ordering Code:
Order Number
DM74AS573WM
DM74AS573N
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006313
www.fairchildsemi.com

DM74AS573N Related Products

DM74AS573N DM74AS573WM DM74AS573
Description Octal D-Type Transparent Latch with 3-STATE Outputs Octal D-Type Transparent Latch with 3-STATE Outputs Octal D-Type Transparent Latch with 3-STATE Outputs
Is it Rohs certified? conform to conform to -
Parts packaging code DIP SOIC -
package instruction DIP, DIP20,.3 SOP, SOP20,.4 -
Contacts 20 20 -
Reach Compliance Code unknow unknow -
series AS AS -
JESD-30 code R-PDIP-T20 R-PDSO-G20 -
JESD-609 code e3 e3 -
length 26.075 mm 12.8 mm -
Logic integrated circuit type BUS DRIVER BUS DRIVER -
MaximumI(ol) 0.048 A 0.048 A -
Number of digits 8 8 -
Number of functions 1 1 -
Number of ports 2 2 -
Number of terminals 20 20 -
Maximum operating temperature 70 °C 70 °C -
Output characteristics 3-STATE 3-STATE -
Output polarity TRUE TRUE -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code DIP SOP -
Encapsulate equivalent code DIP20,.3 SOP20,.4 -
Package shape RECTANGULAR RECTANGULAR -
Package form IN-LINE SMALL OUTLINE -
Peak Reflow Temperature (Celsius) NOT APPLICABLE 260 -
power supply 5 V 5 V -
Maximum supply current (ICC) 106 mA 106 mA -
Prop。Delay @ Nom-Su 6 ns 6 ns -
propagation delay (tpd) 6 ns 6 ns -
Certification status Not Qualified Not Qualified -
Maximum seat height 5.08 mm 2.65 mm -
Maximum supply voltage (Vsup) 5.5 V 5.5 V -
Minimum supply voltage (Vsup) 4.5 V 4.5 V -
Nominal supply voltage (Vsup) 5 V 5 V -
surface mount NO YES -
technology TTL TTL -
Temperature level COMMERCIAL COMMERCIAL -
Terminal surface Matte Tin (Sn) Matte Tin (Sn) -
Terminal form THROUGH-HOLE GULL WING -
Terminal pitch 2.54 mm 1.27 mm -
Terminal location DUAL DUAL -
Maximum time at peak reflow temperature NOT APPLICABLE NOT SPECIFIED -
width 7.62 mm 7.5 mm -

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