STM32G473RCT6 datasheet, PDF - EEWORLD Datasheet

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STM32G473RCT6: DescriptionARM® Cortex®-M4 STM32G4 微控制器 IC 32 位单核 170MHz 256KB（256K x 8）闪存 64-LQFP（10x10）; Categorysemiconductor The embedded processor and controller; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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STM32G473RCT6 Overview

ARM® Cortex®-M4 STM32G4 微控制器 IC 32 位单核 170MHz 256KB（256K x 8）闪存 64-LQFP（10x10）

STM32G473RCT6 Parametric

Parameter Name	Attribute value
category
Maker	STMicroelectronics
series	STM32G4
Package	tray
core processor	ARM® Cortex®-M4
Kernel specifications	32-bit single core
speed	170MHz
Connectivity	CANbus，I²C，IrDA，LINbus，QSPI，SAI，SPI，UART/USART，USB
Peripheral	Undervoltage detection/reset, DMA, I²S, POR, PWM, WDT
Number of I/Os	52
Program storage capacity	256KB（256K x 8）
Program memory type	flash memory
EEPROM capacity	-
RAM size	128K x 8
Voltage - Power supply (Vcc/Vdd)	1.71V ~ 3.6V
data converter	A/D 26x12b; D/A 4x12b
Oscillator type	internal
Operating temperature	-40°C ~ 85°C（TA）
Installation type	surface mount type
Package/casing	64-LQFP
Supplier device packaging	64-LQFP（10x10）
Basic product number	STM32G473

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STM32G473xB STM32G473xC

STM32G473xE

Arm

Cortex

-M4 32-bit MCU+FPU, up to 512 KB Flash, 170 MHz /

213DMIPS, 128 KB SRAM, rich analog, math accelerator

Datasheet

production data

Features

Includes ST state-of-the-art patented

technology

•

Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator) allowing 0-wait-state execution

from Flash memory, frequency up to 170 MHz

with 213 DMIPS, MPU, DSP instructions

•

Operating conditions:

– V

, V

DDA

voltage range:

1.71 V to 3.6 V

•

Mathematical hardware accelerators

– CORDIC for trigonometric functions

acceleration

– FMAC: filter mathematical accelerator

•

Memories

– 512 Kbytes of Flash memory with ECC

support, two banks read-while-write,

proprietary code readout protection

(PCROP), securable memory area, 1 Kbyte

OTP

– 96 Kbytes of SRAM, with hardware parity

check implemented on the first 32 Kbytes

– Routine booster: 32 Kbytes of SRAM on

instruction and data bus, with hardware

parity check (CCM SRAM)

– External memory interface for static

memories FSMC supporting SRAM,

PSRAM, NOR and NAND memories

– Quad-SPI memory interface

•

Reset and supply management

– Power-on/power-down reset

(POR/PDR/BOR)

– Programmable voltage detector (PVD)

– Low-power modes: sleep, stop, standby

and shutdown

– V

BAT

supply for RTC and backup registers

LQFP48 (7 x 7 mm)

LQFP64 (10 x 10 mm)

LQFP80 (12 x 12 mm)

LQFP100 (14 x 14 mm)

LQFP128 (14 x 14 mm)

UFQFPN48

(7 x 7 mm)

WLCSP81

(4.02 x 4.27 mm)

UFBGA121

(6 x 6 mm)

TFBGA100

(8 x 8 mm)

•

Clock management

– 4

48 MHz crystal oscillator

– 32 kHz oscillator with calibration

– Internal 16 MHz RC with PLL option (± 1%)

–

Internal

32 kHz RC oscillator (± 5%)

•

Up to 107 fast I/Os

– All mappable on external interrupt vectors

– Several I/Os with 5 V tolerant capability

•

Interconnect matrix

•

16-channel DMA controller

•

5 x 12-bit ADCs 0.25 µs, up to 42 channels.

Resolution up to 16-bit with hardware

oversampling, 0 to 3.6 V conversion range

•

7 x 12-bit DAC channels

– 3 x buffered external channels 1 MSPS

– 4 x unbuffered internal channels 15 MSPS

•

7 x ultra-fast rail-to-rail analog comparators

•

6 x operational amplifiers that can be used in

PGA mode, all terminals accessible

•

Internal voltage reference buffer (VREFBUF)

supporting three output voltages (2.048 V,

2.5 V, 2.9 V)

•

14 timers:

– 2 x 32-bit timer and 2 x 16-bit timers with

up to four IC/OC/PWM or pulse counter

and quadrature (incremental) encoder input

– 3 x 16-bit 8-channel advanced motor

control timers, with up to 8 x PWM

1/229

www.st.com

November 2021

This is information on a product in full production.

DS12712 Rev 4

STM32G473xB STM32G473xC STM32G473xE

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

Arm

Cortex

-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Adaptive real-time memory accelerator (ART accelerator) . . . . . . . . . . . 17

Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CORDIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Filter mathematical accelerator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21

Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.11.1

3.11.2

3.11.3

3.11.4

3.11.5

3.11.6

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.12

3.13

3.14

3.15

3.16

3.17

Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 28

Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DMA request router (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.17.1

3.17.2

Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 29

Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 29

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.18.1

DS12712 Rev 4

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Contents

3.18.2

3.18.3

3.18.4

STM32G473xB STM32G473xC STM32G473xE

Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Operational amplifier internal output (OPAMPxINT): . . . . . . . . . . . . . . . 31

3.19

3.20

3.21

3.22

3.23

3.24

Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.24.1

3.24.2

3.24.3

3.24.4

3.24.5

3.24.6

3.24.7

Advanced motor control timer (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . 34

General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,

TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.25

3.26

3.27

3.28

3.29

3.30

3.31

3.32

3.33

3.34

3.35

3.36

3.37

3.38

3.39

Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 37

Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Inter-integrated circuit interface (I

C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Universal synchronous/asynchronous receiver transmitter (USART) . . . 40

Low-power universal asynchronous receiver transmitter (LPUART) . . . . 41

Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Controller area network (FDCAN1, FDCAN2, FDCAN3) . . . . . . . . . . . . . 43

Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

USB Type-C™ / USB Power Delivery controller (UCPD) . . . . . . . . . . . . . 43

Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 44

Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 45

Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.39.1

3.39.2

Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 46

Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4/229

DS12712 Rev 4

STM32G473xB STM32G473xC STM32G473xE

Contents

Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

LQFP48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

LQFP80 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

LQFP128 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

WLCSP81 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

TFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

UFBGA121 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.2

5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 82

Embedded reset and power control block characteristics . . . . . . . . . . . 82

Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Wakeup time from low-power modes and voltage scaling

transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 117

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

DS12712 Rev 4

5/229

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