W631GG8KB
16M
8 BANKS
8 BIT DDR3 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
8.1
8.2
GENERAL DESCRIPTION ................................................................................................................... 5
FEATURES ........................................................................................................................................... 5
ORDER INFORMATION ....................................................................................................................... 6
KEY PARAMETERS ............................................................................................................................. 7
BALL CONFIGURATION ...................................................................................................................... 8
BALL DESCRIPTION ............................................................................................................................ 9
BLOCK DIAGRAM .............................................................................................................................. 11
FUNCTIONAL DESCRIPTION ............................................................................................................ 12
Basic Functionality .............................................................................................................................. 12
RESET and Initialization Procedure .................................................................................................... 12
8.2.1
Power-up Initialization Sequence ..................................................................................... 12
8.2.2
Reset Initialization with Stable Power .............................................................................. 14
Programming the Mode Registers....................................................................................................... 15
8.3.1
Mode Register MR0 ......................................................................................................... 17
8.3.1.1
Burst Length, Type and Order ................................................................................ 17
8.3.1.2
CAS Latency........................................................................................................... 18
8.3.1.3
Test Mode............................................................................................................... 18
8.3.1.4
DLL Reset............................................................................................................... 18
8.3.1.5
Write Recovery ....................................................................................................... 19
8.3.1.6
Precharge PD DLL ................................................................................................. 19
8.3.2
Mode Register MR1 ......................................................................................................... 19
8.3.2.1
DLL Enable/Disable ................................................................................................ 20
8.3.2.2
Output Driver Impedance Control ........................................................................... 20
8.3.2.3
ODT RTT Values .................................................................................................... 20
8.3.2.4
Additive Latency (AL) ............................................................................................. 20
8.3.2.5
Write leveling .......................................................................................................... 20
8.3.2.6
Output Disable ........................................................................................................ 21
8.3.2.7
TDQS, TDQS# ........................................................................................................ 21
8.3.3
Mode Register MR2 ......................................................................................................... 22
8.3.3.1
Partial Array Self Refresh (PASR) .......................................................................... 23
8.3.3.2
CAS Write Latency (CWL) ...................................................................................... 23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) ............................. 23
8.3.3.4
Dynamic ODT (Rtt_WR) ......................................................................................... 23
8.3.4
Mode Register MR3 ......................................................................................................... 24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................ 24
No OPeration (NOP) Command .......................................................................................................... 25
Deselect Command............................................................................................................................. 25
DLL-off Mode ...................................................................................................................................... 25
DLL on/off switching procedure ........................................................................................................... 26
8.7.1
DLL
“on”
to DLL
“off”
Procedure .......................................................................... 26
8.7.2
8.8
DLL
“off”
to DLL
“on”
Procedure .......................................................................... 27
Input clock frequency change ............................................................................................................. 28
8.8.1
Frequency change during Self-Refresh............................................................................ 28
8.8.2
Frequency change during Precharge Power-down .......................................................... 28
8.3
8.4
8.5
8.6
8.7
Publication Release Date: Dec. 14, 2015
Revision: A05
-1-
W631GG8KB
8.9
Write Leveling ..................................................................................................................................... 30
8.9.1
DRAM setting for write leveling & DRAM termination function in that mode .................... 31
8.9.2
Write Leveling Procedure ................................................................................................. 31
8.9.3
Write Leveling Mode Exit ................................................................................................. 33
Multi Purpose Register ........................................................................................................................ 34
8.10.1
MPR Functional Description ............................................................................................. 35
8.10.2
MPR Register Address Definition ..................................................................................... 36
8.10.3
Relevant Timing Parameters ............................................................................................ 36
8.10.4
Protocol Example ............................................................................................................. 36
ACTIVE Command.............................................................................................................................. 42
PRECHARGE Command .................................................................................................................... 42
READ Operation ................................................................................................................................. 43
8.13.1
READ Burst Operation ..................................................................................................... 43
8.13.2
READ Timing Definitions .................................................................................................. 44
8.13.2.1
READ Timing; Clock to Data Strobe relationship.................................................... 45
8.13.2.2
READ Timing; Data Strobe to Data relationship ..................................................... 46
8.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................. 47
8.13.2.4
tRPRE Calculation .................................................................................................. 48
8.13.2.5
tRPST Calculation .................................................................................................. 48
8.13.2.6
Burst Read Operation followed by a Precharge...................................................... 54
WRITE Operation ................................................................................................................................ 56
8.14.1
DDR3 Burst Operation ..................................................................................................... 56
8.14.2
WRITE Timing Violations ................................................................................................. 56
8.14.2.1
Motivation ............................................................................................................... 56
8.14.2.2
Data Setup and Hold Violations .............................................................................. 56
8.14.2.3
Strobe to Strobe and Strobe to Clock Violations..................................................... 56
8.14.2.4
Write Timing Parameters ........................................................................................ 56
8.14.3
Write Data Mask............................................................................................................... 57
8.14.4
tWPRE Calculation........................................................................................................... 58
8.14.5
tWPST Calculation ........................................................................................................... 58
Refresh Command .............................................................................................................................. 65
Self-Refresh Operation ....................................................................................................................... 67
Power-Down Modes ............................................................................................................................ 69
8.17.1
Power-Down Entry and Exit ............................................................................................. 69
8.17.2
Power-Down clarifications - Case 1 ................................................................................. 75
8.17.3
Power-Down clarifications - Case 2 ................................................................................. 75
8.17.4
Power-Down clarifications - Case 3 ................................................................................. 76
ZQ Calibration Commands .................................................................................................................. 77
8.18.1
ZQ Calibration Description ............................................................................................... 77
8.18.2
ZQ Calibration Timing ...................................................................................................... 78
8.18.3
ZQ External Resistor Value, Tolerance, and Capacitive loading ...................................... 78
On-Die Termination (ODT) .................................................................................................................. 79
8.19.1
ODT Mode Register and ODT Truth Table ...................................................................... 79
8.19.2
Synchronous ODT Mode .................................................................................................. 80
8.19.2.1
ODT Latency and Posted ODT ............................................................................... 80
8.19.2.2
Timing Parameters ................................................................................................. 80
8.19.2.3
ODT during Reads .................................................................................................. 82
8.19.3
Dynamic ODT .................................................................................................................. 83
8.19.3.1
Functional Description: ........................................................................................... 83
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
Publication Release Date: Dec. 14, 2015
Revision: A05
-2-
W631GG8KB
8.19.3.2
ODT Timing Diagrams ............................................................................................ 84
8.19.4
Asynchronous ODT Mode ................................................................................................ 88
8.19.4.1
Synchronous to Asynchronous ODT Mode Transitions .......................................... 89
8.19.4.2
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry .. 89
8.19.4.3
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit..... 92
8.19.4.4
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods
93
9.
9.1
9.2
9.3
10.
OPERATION MODE ........................................................................................................................... 94
Command Truth Table ........................................................................................................................ 94
CKE Truth Table ................................................................................................................................. 96
Simplified State Diagram ..................................................................................................................... 97
ELECTRICAL CHARACTERISTICS ................................................................................................... 98
10.1 Absolute Maximum Ratings ................................................................................................................ 98
10.2 Operating Temperature Condition ....................................................................................................... 98
10.3 DC & AC Operating Conditions ........................................................................................................... 98
10.3.1
Recommended DC Operating Conditions ........................................................................ 98
10.4 Input and Output Leakage Currents .................................................................................................... 99
10.5 Interface Test Conditions .................................................................................................................... 99
10.6 DC and AC Input Measurement Levels ............................................................................................. 100
10.6.1
DC and AC Input Levels for Single-Ended Command and Address Signals .................. 100
10.6.2
DC and AC Input Levels for Single-Ended Data Signals ................................................ 101
10.6.3
Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ........... 103
10.6.4
Single-ended requirements for differential signals ......................................................... 104
10.6.5
Differential Input Cross Point Voltage ............................................................................ 105
10.6.6
Slew Rate Definitions for Single-Ended Input Signals .................................................... 106
10.6.7
Slew Rate Definitions for Differential Input Signals ........................................................ 106
10.7 DC and AC Output Measurement Levels .......................................................................................... 107
10.7.1
Output Slew Rate Definition and Requirements ............................................................. 107
10.7.1.1
Single Ended Output Slew Rate ........................................................................... 108
10.7.1.2
Differential Output Slew Rate ............................................................................... 109
10.8 34 ohm Output Driver DC Electrical Characteristics.......................................................................... 110
10.8.1
Output Driver Temperature and Voltage sensitivity ........................................................ 112
10.9 On-Die Termination (ODT) Levels and Characteristics ..................................................................... 113
10.9.1
ODT Levels and I-V Characteristics ............................................................................... 113
10.9.2
ODT DC Electrical Characteristics ................................................................................. 114
10.9.3
ODT Temperature and Voltage sensitivity ..................................................................... 114
10.9.4
Design guide lines for RTT
PU
and RTT
PD
....................................................................... 115
10.10
ODT Timing Definitions............................................................................................................ 116
10.10.1
Test Load for ODT Timings ............................................................................................ 116
10.10.2
ODT Timing Definitions .................................................................................................. 116
10.11
Input/Output Capacitance ........................................................................................................ 120
10.12
Overshoot and Undershoot Specifications............................................................................... 121
10.12.1
AC Overshoot /Undershoot Specification for Address and Control Pins: ....................... 121
10.12.2
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins: ......... 121
10.13
IDD and IDDQ Specification Parameters and Test Conditions ................................................ 122
10.13.1
IDD and IDDQ Measurement Conditions ....................................................................... 122
10.13.2
IDD Current Specifications ............................................................................................. 132
10.14
Clock Specification .................................................................................................................. 133
10.15
Speed Bins .............................................................................................................................. 134
10.15.1
DDR3-1333 Speed Bin and Operating Conditions ......................................................... 134
Publication Release Date: Dec. 14, 2015
Revision: A05
-3-
W631GG8KB
DDR3-1600 Speed Bin and Operating Conditions ......................................................... 135
DDR3-1866 Speed Bin and Operating Conditions ......................................................... 136
Speed Bin General Notes .............................................................................................. 137
10.16
AC Characteristics ................................................................................................................... 138
10.16.1
AC Timing and Operating Condition for -11 speed grade .............................................. 138
10.16.2
AC Timing and Operating Condition for -12/12I/-15/15I speed grades .......................... 142
10.16.3
Timing Parameter Notes ................................................................................................ 146
10.16.4
Address / Command Setup, Hold and Derating ............................................................. 149
10.16.5
Data Setup, Hold and Slew Rate Derating ..................................................................... 156
11.
12.
PACKAGE SPECIFICATION ............................................................................................................ 158
REVISION HISTORY ........................................................................................................................ 159
10.15.2
10.15.3
10.15.4
Publication Release Date: Dec. 14, 2015
Revision: A05
-4-
W631GG8KB
1. GENERAL DESCRIPTION
The W631GG8KB is a 1G bits DDR3 SDRAM, organized as 16,777,216 words
8 banks
8 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. The W631GG8KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I.
The -11 grade is compliant to the DDR3-1866 (13-13-13) specification. The -12 and 12I grades are
compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is guaranteed to
support -40°C ≤ T
CASE
≤ 95°C). The -15 and 15I grades are compliant to the DDR3-1333 (9-9-9)
specification (the 15I industrial grade which is guaranteed to support -40°C ≤ T
CASE
≤ 95°C).
The W631GG8KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: V
DD
, V
DDQ
= 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
System level timing calibration support via write leveling and MPR read pattern
Publication Release Date: Dec. 14, 2015
Revision: A05
-5-
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