K7B163625A
K7B163225A
K7B161825A
Preliminary
512Kx36/32 & 1Mx18 Synchronous SRAM
16Mb SB/SPB Synchronous SRAM Ordering Information
Org.
Part Number
Mode
VDD
Speed
SB ; Access Time(ns)
SPB ; Cycle Time(MHz)
6.5/7.5/8.5ns
250/225/200/167/138MHz
250/225/200/167/138MHz
250/225/200/167/138MHz
Q :100TQFP
250/225/200/167/138MHz H : 119BGA
F : 165FBGA
250/225/200/167/138MHz
250/225/200/167/138MHz
6.5/7.5/8.5ns
250/225/200/167/138MHz
250/225/200/167/138MHz
250/225/200/167/138MHz
6.5/7.5/8.5ns
C
(Commercial
Temperature
Range)
PKG
Temp
K7B161825A-Q(H/F)C(I)65/75/85
1Mx18
K7A161880A-QC(I)25/22/20/16/14
SB
SPB(2E1D)
3.3
1.8
3.3
3.3
3.3
1.8
3.3
3.3
3.3
1.8
3.3
3.3
K7A161800A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D)
K7A161801A-QC(I)25/22/20/16/14
K7B163225A-QC(I)65/75/85
512Kx32 K7A163280A-QC(I)25/22/20/16/14
K7A163200A-QC(I)25/22/20/16/14
K7A163201A-QC(I)25/22/20/16/14
K7B163625A-Q(H/F)C(I)65/75/85
512Kx36
K7A163680A-QC(I)25/22/20/16/14
SPB(2E2D)
SB
SPB(2E1D)
SPB(2E1D)
SPB(2E2D)
SB
SPB(2E1D)
I
(Industrial
Temperature
Range)
K7A163600A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D)
K7A163601A-QC(I)25/22/20/16/14
SPB(2E2D)
-2-
Aug 2001
Rev 0.2
K7B163625A
K7B163225A
K7B161825A
Preliminary
512Kx36/32 & 1Mx18 Synchronous SRAM
512Kx36/32 & 1Mx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7B163625A, K7B163225A and K7B161825A are
18,874,368-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pentium
and Power PC based System.
It is organized as 512K(1M) words of 36(32/18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B163625A, K7B163225A and K7B161825A are fabri-
cated using SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP, 119BGA and 165FBGA
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -65
t
CYC
t
CD
t
OE
7.5
6.5
3.5
-75
8.5
7.5
3.5
-85 Unit
10
8.5
4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
A′
0
~A′
1
512Kx36/32 , 1Mx18
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-3-
Aug 2001
Rev 0.2
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