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DM74LS257BM

Description
3-STATE Quad 2-Data Selectors/Multiplexers
Categorylogic    logic   
File Size56KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS257BM Overview

3-STATE Quad 2-Data Selectors/Multiplexers

DM74LS257BM Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Codeunknow
seriesLS
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length9.9 mm
Logic integrated circuit typeMULTIPLEXER
MaximumI(ol)0.024 A
Number of functions4
Number of entries2
Output times1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)19 mA
Prop。Delay @ Nom-Su18 ns
propagation delay (tpd)42 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
DM74LS257B 3-STATE Quad 2-Data Selectors/Multiplexers
June 1989
Revised November 1999
DM74LS257B
3-STATE Quad 2-Data Selectors/Multiplexers
General Description
These Schottky-clamped high-performance multiplexers
feature 3-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a HIGH or LOW logic level. To minimize the pos-
sibility that two outputs will attempt to take a common bus
to opposite logic levels, the output enable circuitry is
designed such that the output disable times are shorter
than the output enable times.
This 3-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL reg-
isters for data retention throughout the system.
Features
s
3-STATE versions LS157 and LS158 with same pinouts
s
Schottky-clamped for significant improvement in A-C
performance
s
Provides bus interface from multiple sources in
high-performance systems
s
Average propagation delay from data input 12 ns
s
Typical power dissipation: 50 mW
Ordering Code:
Order Number
DM74LS257BM
DM74LS257BN
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Function Table
Inputs
Output
Control
H
L
L
L
L
H
=
HIGH Level
L
=
LOW Level
Output Y
A
X
L
H
X
X
B
X
X
X
L
H
LS257
Z
L
H
L
H
Select
X
L
L
H
H
X
=
Don’t Care
Z
=
High Impedance (off)
© 1999 Fairchild Semiconductor Corporation
DS006417
www.fairchildsemi.com

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DM74LS257BM DM74LS257 74LS257 DM74LS257B DM74LS257BN
Description 3-STATE Quad 2-Data Selectors/Multiplexers 3-STATE Quad 2-Data Selectors/Multiplexers 3-STATE Quad 2-Data Selectors/Multiplexers 3-STATE Quad 2-Data Selectors/Multiplexers 3-STATE Quad 2-Data Selectors/Multiplexers

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